People have been talking about “More than Moore” for some time now. I think that 2016 is the year that this theme will actually start picking up momentum. Another aspect of the process landscape is that nodes older than 28nm are maturing and gradually declining in cost per gate. The FinFET process, even with its area, power, and performance advantages, may still not be justified for many types of applications. However, the adoption of FinFET technology has far outstripped many of the pessimistic prognostications.
These changes mean that a much richer menu of options will be open to design groups for implementation. It will be more important to evaluate these choices well and get the architecture of the design correct. This will require a holistic view of the design from software down through silicon to packaging. This is what we, at Cadence, call System Design Enablement (SDE).
When people say “More than Moore,” they are referring to ways to increase the density and decrease the size of their designs via methods other than simply scaling the transistors. For a long time, the leading solution for this has been to use multiple die on silicon interposers. Over the last decade, there have been many different ways to package multiple dies together. The newest process technology that increases density is the through silicon via (TSV), a copper plug that goes through the back of the wafer and is exposed when the wafer is thinned.
The good thing about 3D interposer-based design is that high performance and potentially huge scaling are possible. There have been several technology variations of the original 3D interposer-based design to make them more affordable. We have started to see the different types of offerings at different price points for different types of applications. Still, these new technologies are generally not cheap, and they come with more complicated business models to address bare dies from different sources. So, it’s essentially a large player’s game to address markets that require the high performance and scale.
Next year, we should see lower cost consumer 3D packaging approaches go into volume production without requiring interposers or TSVs. I expect that by the end of 2016, many high-end smartphones will be using this technology. Since smartphone models ship in hundreds of millions of units, this will instantly create a volume ramp and, of course, there will be learning and yield. Once the early adopters start using this approach, the technology will go mainstream and be available to address lower volume markets such as automotive or Internet of Things (IoT).
A second big change is that over the last few years, we’ve seen a shift in the way process nodes are used. Up until 90nm or so, every digital design moved to the new process as soon as possible because cost, power, and performance were all consistently better. Nobody wanted to be caught a process generation behind their competition at a higher price point with worse power and less performance. Since then, the economics of moving to a new node have changed. As a result, companies make these transitions based on target applications. We’ve seen many companies with mixed choices of processes. Sometimes, they stay with derivative processes at several larger nodes for different applications.
In response, foundries have been taking the knowledge they have gained in advanced nodes and have applied it into other processes—specialized low-power processes, non-volatile memory, lower price-point consumer processes, and so on.
There have been changes in the end markets, too. The explosion of electronics in automotive is significant, particularly with the evolution of infotainment and driver assist capabilities. Previously, automotive was not known to be on the leading edge for reliability reasons, not to mention its very long qualification cycle. Computer, communication, and mobile markets continue to charge forward with FinFET technologies, while the process choices for the diverse IoT type of designs are likely to be driven based on applications.
In fact, FinFET is being adopted much faster than expected by a wide range of customers. In addition, 10nm designs are in progress, and work is well underway on 7nm. There have even been experimental tapeouts of interconnect at 5nm. The tradeoffs in manufacturing techniques (e.g., EUV with multi-patterning) with new device structures and new materials will be driven by the leading foundry players. As partnerships line up, there may be some dramatically different choices that are made starting next year and, of course, beyond.