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SYKATIYA Technologies Hiring High-Speed SerDes Design Engineers with minimum of 2+ to 15 years working experience in TX, RX, Common lane (PLLs, LDO, Biasing and clock buffers) Positions: Junior/Senior/Lead/Manager position offered Job Descriptions Any process nodes design experience preferred Good cadence...
Looking for Analog Circuit Design Engineer Notice Period: 0-60 days Experience: 2 years to 10 years Note Few onsite opportunities are available for the people who are ready to join immediately (min 5 years Analog Design Experience). Location: Bengaluru Company: Sykatiya Technologies Private Limied Please share...
Experience level: 3-8 years Good experience in handling Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS Experience in handling analog layout of Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Strong...

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