Saturday, May 18, 2024

How Cores Impact Communications Within SoCs

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For systems-on-chip (SoCs) with moderate number of cores, crossbar interconnects are typically used for intra-chip communication. However, as the number of cores increases, network-on-chip (NoC) is a promising solution.

In that case, what are the steps being taken to address this issue? As per Freescale, the architectural features like multi-level clustered memory hierarchy, interconnect architecture solutions ranging from point-to-point interconnect and NoC are employed, depending on SoC requirements. NoCs provide a scalable solution for intra-chip communication in high-throughput multimedia platforms.

The number of processing engines will explode in the next few years. How does the industry plan to level out or combat this issue?

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According to Freescale, from a compute engine perspective, heterogeneous architectures employing CPU, GPU, DSP and dedicated hardware accelerators should be preferred. These provide much higher power efficiency than using a homogeneous computing platform of large number of cores. They also require lower interconnect and DDR bandwidth. From an interconnect perspective, NoC is a promising solution.

From a software solution standpoint, parallel partitioning of application in a way that improves performance and controls power budgets is perhaps the biggest challenge. This issue needs to be addressed as part of software architecture and high-level design.

SoC design moving to platform reuse?
Is the SoC design moving from IP or blocks reuse to platform reuse, to minimise software development efforts for time-to-market reasons? With the ability to pack more transistors per die, reuse naturally moves to a higher level to keep design, integration efforts manageable and scalable.

In the multi-/many-core era, one of the biggest challenges is to utilise these cores efficiently in software. On a typical embedded platform used in 3G/4G wireless communication, software development requires more time than building the hardware chip. Hence platform reuse is important to minimise time to market.

So, are we now seeing an advent of the network-on-chip, rather than SoCs? As per Freescale, the SoC is the end goal and the NoC is one means of achieving communication between the elements of the system. The NoC is currently treated as another IP in the SoC design flow, which can be tuned by the system architect according to the requirements of the SoC.

One would like to know the association of the asynchronous GALS with dynamic voltage and frequency scaling (DVFS). A globally asynchronous locally synchronous (GALS) based design style fits nicely with the concept of voltage-frequency islands (VFI). A large SoC is partitioned into several VFIs, each with its own voltage and clock distribution. Hence the DVFS technique can be easily applied to each VFI, wherein at times of lower performance requirements, the voltage and frequency of the island can be reduced to save power.

One would also be keen to find out the limitations of classical NoC-based architectures, if any. As per Freescale, any interconnect style, including NoC, needs to be architected with due considerations to performance requirements like latency, bandwidth and QoS and implementation considerations like die area, congestion and power.

The extra layer of packet processing in an NoC introduces some delay in the interconnect. The system architect should analyse the performance requirements thoroughly before deciding on an NoC topology.

Moving to asynchronous communications
In the current deep sub-micron technologies, it is difficult to route signals across a die in a single clock cycle and in a power-efficient manner. This makes clock tree synthesis and timing closure challenging. Therefore global asynchronous communication across multiple IPs is a promising solution.

Current chips invariably employ various levels of local and global clock gating to reduce power in IPs. Local clock gating is used for few flip-flops, whereas global clock gating is used to shut off the entire IP (or large modules in it) based on usage. More aggressive low-power techniques include power-shutdown and DVFS for IPs with independent voltage-frequency domains.

The NoC needs to be aware of such voltage domain crossings so as to insert appropriate level shifters. NoCs need to use mixed-clock/mixed-voltage interfaces (FIFOs) to communicate across different voltage and frequency domains.


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