Sudeep Shivalli of Synopsys India tells EFY’s Nidhi Agarwal why great chip design is only the first step in building a successful product.
On opportunity and execution
Q. Where are the biggest opportunities for Indian chip designers today?
A. India has a strong semiconductor design ecosystem, with many global chip companies running large engineering and design centres in the country. These teams are already working on advanced chip designs across areas such as data centres, artificial intelligence (AI), edge AI, and automotive electronics, creating significant opportunities for engineers and design teams.
From an industry perspective, three major trends are shaping the market: AI, software-defined systems, and silicon proliferation. The last is particularly relevant to India. As more sectors adopt specialised semiconductor solutions, demand is growing for chips tailored to railways, cameras, ships, industrial equipment, and other locally developed systems. Government initiatives encouraging domestic design and development in these sectors are also opening up new opportunities for Indian semiconductor teams to contribute to products designed and built in India.
Q. What are the biggest challenges in taking a chip from design to production in India?
A. One of the biggest challenges is developing a clear product strategy. Companies need to decide which markets they want to serve, define their product lines, and create a roadmap for scaling their business. Although investment opportunities have improved thanks to research and deep-tech funding initiatives, attracting capital still depends on a strong go-to-market plan. Chip development also demands significant upfront investment, specialised expertise, and strong ecosystem partnerships, which sets it apart from software development.
A second challenge is building a strong domestic market for locally designed chips. Greater adoption across sectors such as transportation, consumer electronics, aerospace, and security can help companies establish sustainable product lines while remaining globally competitive. Finally, while India’s semiconductor manufacturing ecosystem is growing, companies developing advanced chips still rely heavily on global foundries, making international manufacturing partnerships critical for moving designs from concept to silicon production.
Q. What challenges do startups in India face when bringing silicon products from concept to tape-out?
A. The first challenge is securing a strong go-to-market strategy, adequate funding, and ideally an anchor customer who believes in the product idea, as many startups struggle to cross this initial business hurdle. Once that is addressed, finding the right talent becomes critical. Chip development requires engineers with a system-level understanding who can visualise what the chip needs to achieve electronically and translate those goals into silicon, rather than simply executing individual tasks within an engineering project. The third major challenge is managing risks related to time-to-market, tape-out schedules, and execution. Tape-out is not the finish line—it’s where the real validation begins.
On fabs and nodes
Q. What technical challenges must new fabs overcome before reaching stable high-volume production?
A. One of the biggest challenges for a new fab is achieving high yield, which is a key measure of manufacturing success. Yield is the percentage of chips on a wafer that function correctly, and reaching 98-99 per cent requires multiple rounds of prototyping, testing, and optimisation. From a design perspective, the process begins with transistor development, followed by IP creation and test chip fabrication. These test chips are then manufactured and tested, and the resulting post-silicon data is used to refine the design and production flow.
At the same time, a fab depends on a much larger ecosystem involving equipment, materials, gases, chemicals, and manufacturing processes, all of which must work together reliably. Because of this complexity, bringing a fab to stable high-volume production is a long and systematic effort. It requires continuous tuning across multiple stages and cannot be achieved quickly just by setting up a manufacturing facility.
Q. How is the market split across technology nodes, and what does that mean for design?
A. Looking at technology nodes, a large share of chips in the market is still built on mature nodes. Around 60 to 65 per cent of chips use mature nodes, which here means 12 nm up to 28 nm (for example, 12, 16, 20 and 28 nm). Only about 35 per cent of the market is at the cutting edge; within that, truly advanced nodes—around 2 nm and below—account for just 2 to 3 per cent. These leading-edge designs are mainly used in high-end data centre and mobile applications, where advanced performance is required. These figures are consistent with public industry data, and they show that semiconductor design continues to evolve across both mature and cutting-edge nodes rather than shifting entirely to the newest technology.
On below 3 nm and beyond
Q. What new design challenges emerge when moving below 3 nm?
A. Moving below 3 nm into angstrom-based design shifts the challenges considerably. Higher transistor density packs more devices into the same area, raising power density and intensifying thermal issues and mechanical stress inside the chip. Power delivery becomes more complex, especially in how power grids are designed to support fast transistor switching without instability.
Engineers must therefore go beyond the traditional focus on area, power, and cost seen in mature nodes and analyse many more interacting factors such as power, performance, thermal behaviour, noise, stress, and cooling. This also requires more advanced methods like dynamic voltage and thermal analysis, and even cooling must be modelled as part of the chip design itself. In short, design below 3 nm adds multiple tightly coupled variables that need deep, simultaneous optimisation.
Q. What EDA innovations do gate-all-around (GAA) transistor architectures need, and which technology areas are driving EDA demand in India and globally?
A. Electronic design automation (EDA) innovation for GAA architectures is mainly focused on how libraries are designed and implemented. IP teams develop embedded memory and logic libraries for different foundries across technologies like FinFET and GAA, and the key challenge is ensuring that all foundry-specific design rules are correctly handled by the tools during implementation.
At the same time, major demand for EDA solutions comes from highly complex, cutting-edge designs, both in India and globally. These include Arm-based systems, which are becoming ever more complex, and high-speed interfaces such as universal chiplet interconnect express (UCIe) and advanced memory interfaces that need very fast data transfer. Such systems also involve building subsystems with multiple IPs and integrating them with processors—sometimes 20, 30, or even more—while running different workloads. The challenge, therefore, is not just about advanced technology nodes but also about managing increasing system-level complexity, integration, and verification across the full design stack.
On the chiplet era
Q. Will chiplets eventually replace large monolithic systems on chips (SoCs) for most high-performance applications?
A. Yes, in many high-performance applications, chiplets are expected to overtake large monolithic SoCs. There is also work on wafer-scale approaches, where an entire wafer is treated as a single system, especially in data centre use cases. The shift is mainly driven by reuse and the ability to scale product lines more efficiently. However, the choice still depends on whether a customer wants a multi-die solution or a full wafer-scale chip, since wafer-scale systems are expensive to handle and bring several second-order system effects. Overall, for domains like data centres, the trend is clearly towards multi-die chiplet-based designs rather than large monolithic SoCs.
“Engineers must go beyond the traditional focus on area, power, and cost seen in mature nodes and analyse many more interacting factors such as power, performance, thermal behaviour, noise, stress, and cooling.”
Q. How are advanced packaging technologies changing the relationship between design and manufacturing?
A. Advanced packaging technologies have made design and manufacturing much more interconnected. Today, it is a continuous ‘correct-by-construction’ process in which both teams exchange data and models throughout development. Design teams provide specific formats and information to packaging engineers, while packaging teams supply models that help designers perform analysis and optimisation. Some improvements are made at the design stage, while others are handled during packaging.
Because packaging decisions affect factors such as form factor, pin count, current-carrying capacity, and overall system requirements, packaging must be considered very early in the development cycle, often when the specification or RTL is being defined. The package architecture needs to be largely finalised before many design decisions can be completed. As a result, design and manufacturing are no longer isolated functions; they operate as an integrated process, with close collaboration from the beginning of the project.
Q. What verification challenges emerge when moving from single-die design to chiplet-based architectures?
A. The main challenge is ensuring correct system-level behaviour across the full chiplet architecture, including power-up sequencing, high-speed interfaces, and workload execution for cloud-level use cases. To address this, hardware-assisted verification (HAV) is used, in which the full chip is modelled on platforms like ZeBu before silicon is available. This allows customers to run real workloads pre-silicon, including complex AI and large language models (LLMs) as well as smaller software workloads, and observe system behaviour early. The process helps identify issues and guide design improvements before tape-out, and continues iteratively until the chip is ready. Once silicon is available, the same workloads can be run again on the actual hardware to confirm real-world performance and correctness.
On the engineer’s toolkit
Q. What new skills should semiconductor engineers develop to work effectively with AI-enabled design tools?
A. From an engineer’s point of view, strong fundamentals remain essential. There is no shortcut around understanding how transistors work, how digital design fundamentals and logic gates operate, and what design trade-offs need to be addressed. At the same time, engineers should avoid becoming purely task-focused and instead develop knowledge of protocols and systems. Since chips ultimately go into applications such as mobile devices, surveillance cameras, and other intelligent systems, engineers need to understand the broader system context and how a design can be improved for its end use. Innovation increasingly happens across domains, which is why fundamentals, systems thinking, and protocol knowledge matter.
The approach to workforce development is also changing. Rather than simply learning how to use a tool, engineers should focus on what they want to achieve with it. The key question is not how to use the tool, but what problem they are trying to solve with it—a mindset that all engineers should adopt.
