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Location: Bengaluru
Company: IBM
Introduction
The High Speed IO design team delivers both proprietary and industry-standard interfaces for IBM’s POWER systems’ and Z Mainframe’s processors. With a current data rate up to 64Gbps and rising, verifying the functionality of the digital and analog components in an efficient manner is necessary.
Your Role And Responsibilities
- Understand the design specification, Power On Specification, and Power management specification.
- Understand boot firmware and reset flow. And/or Power management flow.
- Develop skills in verification tools and apply them successfully
- Develop the verification environment and test bench
- Debug fails using waveform, trace tools and debug RTL code
- Work with Design team in resolving/debugging logic design issues and responsible for deliveries
- Running regression checks and coverage analysis
Required Education
Bachelor’s Degree
Preferred Education
Master’s Degree
Required Technical And Professional Expertise
- Experience in Design Verification – demonstrated execution experience of the verification of logic blocks
- Strong in SoC verification: Chip reset sequence and initialisation, and/or Power management.
- Knowledge of verification (any) methodology, Knowledge of HDLs (VHDL, Verilog)
- Good programming skills in C++/C, Object Oriented Programming(OOPs), Python/Perl
- Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails
- Hardware debug skills backed by relevant experience on projects
- Exposure in developing testbench environment, write complex test scenarios
- Good communication skills and be able to work effectively in a global team environment
- Drive verification coverage closure
Preferred Technical And Professional Experience
- Knowledge of High Speed Serdes Phy Interface, PCIe, Ethernet, DDR
- Knowledge of Chip-Initialisation, SCAN, and BIST is a plus
- Scripting Expertise backed up by relevant experience in the same
- Writing Verification test plans
- Functional and code coverage analysis and debug
