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- Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.
- Responsible to implement and analyze system Verilog assertion and coverage(code, toggle, functional) .
- Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue.
- Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks.
- Adhere to quality standards and good test and verification practices.
- B.E/B. Tech/M.E/M. Tech in electronics with 2+ years experience in verification domain
- Prior work experience on IP level or Soc level.
- Prior work on UFS (Universal Flash Storage),Ethernet and PCIe Protocol is desirable.
- Good understanding of processor based Soc level verification which includes native ,Verilog ,system Verilog and UVM mix environment.
- Hand on experience with verification tools such as VCS, waveform analyzer and third party VIP integration (such as Synopsys VIPs).
- Hands on experience in UVM. C/C++ ,System Verilog verification language.
- Good understanding of AXI-AMBA protocol variants.
- Can work with scripting language (shell, Makefile, Perl )
- Strong understanding of design concepts and ASIC flow.
- Good problem solving , analytical and debugging skill is must.