The position is an exciting opportunity to be part of a flexible and dynamic team in the growing markets of mixed signal chips with signal processing IPs, ARM processor and AMBA bus interface like Wireless Chargers, Bluetooth, PMIC etc. used in Mobile, Tablets, Microcontrollers etc.
The role works within the digital verification team in Greater Noida collaborating with the design and verification teams in Italy and Singapore creating SV UVM based verification environment, using various apps of JasperGold to ensure design quality and qualify the testbench using Certitude.
- Work on IP verification or SOC verification.
- Verification planning using v-plan, functional points identification, and review.
- SV UVM based test-bench development.
- Implementation using different verification techniques (constraint random dynamics simulation and static formal verification).
- Verification closure by ensuring 100% code and functional coverage.
- Schedule preparation and execution adhere to plan.
- Present reports to the management.
- Masters in Electronics’ Engineering (a relevant experience with minimum 4 years in a semiconductor or high technology R&D environment would be appreciated)
- Experience in Hardware Design Language (such as VHDL or Verilog).
- Experience in Digital verification with various skill sets:
(a) Universal Verification Methodology (UVM)
(b) System Verilog (SV)
(c) C/C++ language, preferably with ARM CORTEX processor
(d) Formal Methodology (Jasper GOLD)
(e) Scripting languages (PERL, TCL, PYTHON)
- Good communication and written skills in English.
- Able to work in a multi-cultural team.
- Strong analytical and problem-solving skill.Able to keep up with fast moving new verification methodology.
Qualification: BTech/MTech – Min 70%
Experience: Min 3 years Max 8 Years