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Location: Bengaluru
Company: Tejas Networks
The FPGA Design Engineer with 2-4 years of experience will be responsible for the development of Open RAN (ORAN) radio systems. The role involves translating system‑level wireless and ORAN requirements into FPGA architectures, implementing RTL designs, integrating IPs, and optimising high‑performance digital signal processing blocks. The engineer will also participate in simulation, verification, timing closure, and hardware bring‑up activities on target platforms.
Responsibilities
- Design and develop FPGA-based solutions for radio systems.
- Have a general understanding of ORAN 4G and 5G radio access networks, E-CPRI protocols, and related specifications.
- Develop based on IP modules of signal chain processing. – Have experience in antenna array steering, beamforming, and TDD waveforms.
- Familiarity with AMD Xilinx SoC (MPSoC/RFSoC) and Intel FPGA families.
- Participate in system-level design and optimisation.
- Debug and troubleshoot FPGA designs.
- Expertise in FPGA timing constraints and timing closure, clock domain crossing, and design implementation for Intel FPGA/AMD Xilinx FPGA.
- Work closely with cross-functional engineers to integrate FPGA designs into the larger ORAN system.
- Develop and implement testing procedures to ensure quality control and reliability of FPGA-based solutions.
Mandatory Skills
- Experience with ORAN/4G/5G Radio Related technologies and standards
- Familiarity with RF and communication systems is a plus
- Strong analytical and problem-solving skills
- Excellent communication and teamwork skills
- 4+ years of experience in FPGA design and implementation. Strong development experience with Verilog
- Knowledge of Digital Signal Processing
Desired Skills
- Experience in RF communication systems, Software-defined radio, and related technologies
- Experience with high-speed protocol such as 10/25/100 Gbit/s (SFP+, QSFP+) Ethernet, PCIe etc.
- Knowledge of LTE/5G stack and standards,
- C, C++, Python, MATLAB, Linux, Bash.
- Embedded system design
- CI/CD and GIT,
- ARM bare-metal firmware design
Qualifications
- Experience: 2 -4 years of experience in FPGA design and implementation. Strong development experience with Verilog
- Education: BE / B. Tech / M. Tech – ECE/EEE
