Wednesday, June 19, 2024

STA Engineer At Apex Semiconductor

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Location: Bangalore, Noida and Coimbatore

Company: Apex Semiconductor

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You will own the block and chip level STA analysis and methodology for high performance and low power designs as well as complex SOCs.


  • Block level and chip level timing analysis.
  • Timing analysis of different kinds of interfaces at chip level.
  • Work with the design and implementation teams to develop and qualify timing constraints.
  • Work on methodology development for timing analysis and timing closure.
  • Contribute to the STA flow development.
  • Work closely with the physical design engineers to resolve implementation related timing issues.
  • Create methodologies for customized timing checks for different IPs, interfaces etc.
  • Validation of library timing data (qualification of libraries).


  • BTech/MTech from a reputed university.
  • 2-4 years of hands-on experience in timing analysis.
  • Experience in doing SoC level timing analysis.
  • Should be familiar with timing analysis for hierarchical designs.
  • Familiarity with different types of interfaces like PCIe, SATA, USB, DDR etc.
  • Worked on technology nodes 16nm and 7nm.
  • Proficiency in industry standard STA tools (Tempus and PrimeTime).
  • Good scripting skill in Tcl and Python.
  • Familiarity with different physical design tools preferably Cadence Innovus.


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