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- 7+ years working experience in memory Design, characterization and FE Model generation (timing, power).
- Good experience in Circuit design and able to come up with innovative circuit solution to achieve the best in class PPA
- Experience in using industry standard schematic entry tools, advanced transistor level simulators (XA, HSIM, FINESIM)
- Experience in developing Memory Compiler, characterization and modeling
- Ability to come up with design verification and test plans
- Good working knowledge of scripting language (Perl, Shell scripts).
- Basic understanding of HDL language (Verilog, RTL).
- Knowledge of advanced nodes (7nm/5n FF) would be preferable
- Exposure to LEC tools will be preferred
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