Company: Western Digital
The future. It’s on you. You & Western Digital.
We’ve been storing the world’s data for more than 50 years. Once, it was the most important thing we could do for data. Now we’re helping the world capture, preserve, access and transform data in a way only we can.
The most game-changing companies, consumers, professionals, and governments come to us for the technologies and solutions they need to capture, preserve, access, and transform their data.
But we can’t do it alone. Today’s exceptional data challenges require your exceptional skills. It’s You & Us. Together, we’re the next big thing in data.
Western Digital data-centric solutions are found under the G-Technology, HGST, SanDisk, Tegile, Upthere, and WD brands.
- Handling block layouts like Charge Pumps, I/O’s, Reference generators
- Involve in the full chip Signal/Power planning, die size estimation.
- Interact with project lead (design and layout) and CAD for various requirements
- Work with the project lead on chip level integration task and tape out procedures
- Schedule planning of the assigned task.
- Person will be working with our India and US physical design teams for all tasks.
- Mentor junior team members
- Experience in Cadence Platform
- Knowledge of layout concepts like Matching, shielding, Symmetry, ESD, latch-up, Reliability and DFM
- PDK and rule-set development understanding
- Full chip development and tape out flow
- Working experience in blocks like high speed IO, Charge pumps, Regulators, semi-custom blocks etc.
- Scripting knowledge a plus: PERL and SKILL
- Good communication (written and verbal) and interpersonal skills
- Excellent working ability with circuit design and layout methodology development teams
- Excellent problem-solving skills