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Location: Noida

Company: DesignNex

Key Responsibilities

Implementation with emphasis on Physical Verification & Hard macro/core finishing activities.
Must have led and been primarily responsible for physical verification checks , fixing and sign-off.
Excellent understanding of Physical Verification flow with in-depth experience in analysing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues. (Mostly working on Calibre tool)
Deep understanding of ESD, latch-up etc.
Own and execute PV activities at the Top/Block level.
Work closely with PD team in addressing their PV issues and suggest solutions to them.
Work with CAD team in refining the existing flows/methodologies and resolving the issues.
Experience in IO, Bump planning and RDL routing Strategy is a plus.
Develop and implement timing and logic ECOs is a plus
Innovus/FC level DRC fixing is a plus
Python, PERL/TCL knowledge is a plus.
Ability to plan and work independently and coordinate with cross-functional teams
Has ability to close sign off DRC based on PNR markers is plus

Experience with physical verification checks DRC, LVS, Antenna, ERC, PERC, ESD etc.
Experience in PnR tools like ICC/Innovus with regards to physical convergence must.
Understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre and ICV.
Good overall understanding of the Custom IC design flow.
Good understanding of layouts and overall backend tool flow would be beneficial.
Understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre and ICV.
TCL/PERL Scripting is plus.
Hands-on experience: Innovus/Fusion Compiler, Tech lef is preferable.
People management /Floorplanning/Power Planning/PDN experience is BIG Plus