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Location: Noida
Company: STMicroelectronics
In this role candidate will be responsible for overall chip development schedule and project plans, while being able to evaluate technical challenges and concepts and associated risks, challenging and negotiating different functions for seamless and most efficient development cycle while granting right quality deliverables. Design lead will also coordinate with multiple teams like analog IP team, foundation IP’s and libraries team for I/O’s, memories etc. incl 3rd party vendors, digital IP team to define and build block specifications, deliverables, collaterals etc.
Responsibilities
Drive architecture & application teams in converging to an optimal specification from a performance, design effort/cost point of view. This includes detailed technical discussions and evaluations on IP choices and specifications, SoC architecture definitions covering different core and memory subsystems, solutions for clocking, power management, interconnect etc with target of PPA optimization to grant a competitive balance between product features and time-to-market.
- Close engagement with systems teams and customer interfaces to enable correct design decisions while working to build and develop system-level knowledge within the design team.
- Conducts analyses covering feasibility studies, risk analysis, power, die size estimation etc.
- Drive design implementation functions including sub-groups for RTL development and top integration, verification, performance evaluation and pre-Si validation, DFT, and physical implementation team for execution of entire RTL2GDS flow.
- Running weekly reviews of open issues across development functions, closely monitoring and tracking, and provide technical leadership to individuals from outside the function and owning the outcome of the project
- Manage project-related activities like design team meetings, project status reporting, project reviews in compliance with product development lifecycle.
- Collaborates with the teams across project core team members like engineering, validation, packaging, quality & reliability, marketing etc.
Technical Skills/Background
- Qualification: Bachelors/Masters in Electronics/Electrical Engineering
- Experienced about system applications on aspects related to architectural choices in order to optimize for device performance, power and area.
- Good knowledge and understanding of advanced ARM real-time and application CPU cores and memory subsystems, system bus architectures (like AHB/AXI), Arteris NOC and other interconnect technologies, debug subsystems, critical aspects like SoC clocking, reset and power mgmt., high speed SerDes, analog integration, RTL design and SoC integration with multiple asynchronous clock domains, bottlenecks identification, timing issues anticipation and resolution.
- Competent on power and clocking architectural concepts, capable of driving their definitions and anticipate potential implementation issues for high-frequency designs.
- Design experience in mid-high complexity product developments in FDSOI 28nm, 16 FFC, 7nm technology nodes.
- Knowledge of Automotive Functional Safety ISO26262 is a plus.
