Interactive Analog/Digital Mixed Signal Modeling via Foreign VHDL/Verilog C Interface

‘X.c’ is the stand alone C code that implements the model.

Other files from Matlab installation path are also used for code generation and execution.

In particular, the file ‘grt_main.c’ contains the main C routine used to initialize all the variables, to allocate memory, invoke the functional routine that implements the model and terminate the program.

In order to simplify the above procedure, selecting ‘Create Visual C/C++ Solution File for the grt target’ a project file referring all required C/C++ files and settings is generated and ready to be imported in Visual Studio.

ModelSim Language Interface

In order to interface the generated code with VHDL, Visual Studio project and ‘grt_main.c’ file need to be modified, according to Modelsim FLI specifications.

Before starting to create a FLI application, the following additional concepts have to be better cleared.

A foreign VHDL architecture is a design unit that is instantiated in a design but that does not (generally) contain any VHDL code. More likely it is a link to a C model that can communicate with the rest of the design through the ports of the foreign architecture.

FLI routines are C functions providing procedural access to information within Model Technology’s HDL simulator, like Modelsim. A user-written application can use these functions to traverse the hierarchy of an HDL design, get information about and set the values of VHDL objects in the design, get information about a simulation and control a simulation run. The header file, ‘mti.h’ implements all functions and types that can be used by FLI applications and must be included in the modified ‘grt_main.c’.

When the simulator starts, it first goes through an elaboration phase during which the entire design is loaded, connected and initial values are set. During this phase, all foreign shared libraries are loaded and the initialization functions of all foreign architectures are executed.

The simulation phase begins when the first run command is executed and continues until a quit or restart command is executed. When a restart command is executed, the simulator goes through its elaboration phase again.

To use the foreign language interface with C models, VHDL architecture must be first created and compiled with the suited FOREIGN attribute containing the name of the initialization function (‘app_init’) and the path of the shared object file to be loaded (‘app.so’).

The 1st step from the C side for modelsim FLI is to modify configuration parameters in Visual Studio project, according to the following steps:

• Change configuration type to ‘Dynamic library (.dll)’
• In C/C++\general pane, add ‘\include’ to ‘Additional include directories’.
• In linker\general pane, set output file to ‘app.so’
• In linker\Input pane, add ‘\win32\mtipli.lib’ to ‘Additional dependencies’.
• In linker\command line pane, add: ‘-export: app_init’ to ‘Additional options’.

The next step is to modify the main function in ‘grt_main.c’, according to the declaration of an initialization FLI function.

The drawback of this solution is that it uses functions of a specific proprietary (Mentor, Cadence, Synopsys…) and then it is suitable only for that proprietary. In order to simulate the same system with another digital simulator, it is required to write a different FLI or VHPI, based on simulator reference (due to a lack of FLI/VHPI standardization). In the following, an alternative solution based on verilog PLI, that is suitable for almost every digital simulator.

The 1st step from the C side for PLI is to modify configuration parameters in Visual Studio project, according to the following steps:

• Change configuration type to ‘Dynamic library (.dll)’
• In linker\general pane, set output file to ‘app_vpi.sl’
• In linker\command line pane, add: ‘-export:vlog_startup_routines’ to ‘Additional options’.

The second step is to write a C language ‘calltf’ routine that will be called when the Verilog simulator executes the ‘$app_vpi’ system task.

The third step in creating a new PLI application is to notify the Verilog simulator about the new system task or system function name and the C routines which are associated with the application (‘register’ routine).

Optionally a ‘compiletf’ routine can be defined to verify that the system task or system function is being used correctly and has the correct types of arguments.

Finally, the ‘app_interface’ routine (defined in ‘calltf’) reads the inputs, calls the C model ‘rt_onestep’ included in ‘grt_main.c’ and writes outputs to Verilog signals.

Test Case

The above presented procedure has been adopted for developing a simulation environment including STMicroelectronics Intelligent Power and Smart Power models devices for automotive applications. In the specific test case, the application schematic of a LEDs driver L99LD01 has been reproduced, including the external circuitry (Fig. 3).

Initially, the entire simulation schematic was developed in Matlab/Simulink (+SimPowerSystems+ EDA Simulator Link). The digital core was co-simulated by Modelsim.

In a further step, the related C Code has been generated by means of Simulink Coder and compiled. At the same time, a suitable PLI interface has been realized.