While driving on highways, motorists should not exceed the maximum speed limit permitted for their vehicle. However, accidents keep occurring due to speed violations since the drivers tend to ignore their speedometers. This speed checker will come handy for the highway traffic police as it will not only provide a digital display in accordance with a vehicle’s speed but also sound an alarm if the vehicle exceeds the permissible speed for the highway.
The system basically comprises two laser transmitter-LDR sensor pairs, which are installed on the highway 100 metres apart, with the transmitter and the LDR sensor of each pair on the opposite sides of the road. The installation of lasers and LDRs is shown in Fig. 1. The system displays the time taken by the vehicle in crossing this 100m distance from one pair to the other with a resolution of 0.01 second, from which the speed of the vehicle can be calculated as follows:
As per the above equation, for a speed of 40 kmph the display will read 900 (or 9 seconds), and for a speed of 60 kmph the display will read 600 (or 6 seconds). Note that the LSB of the display equals 0.01 second and each succeeding digit is ten times the preceding digit. You can similarly calculate the other readings (or time).
Speed checker circuit diagram
Figure below shows the circuit of the speed checker. It has been designed assuming that the maximum permissible speed for highways is either 40 kmph or 60 kmph as per the traffic rule.
The circuit is built around five NE555 timer ICs (IC1 through IC5), four CD4026 counter ICs (IC6 through IC9) and four 7-segment displays (DIS1 through DIS4). IC1 through IC3 function as monostables, with IC1 serving as count-start mono, IC2 as count-stop mono and IC3 as speed-limit detector mono, controlled by IC1 and IC2 outputs. Bistable set-reset IC4 is also controlled by the outputs of IC1 and IC2 and it (IC4), in turn, controls switching on/off of the 100Hz (period = 0.01 second) astable timer IC5.
The time period of timer NE555 (IC1) count-start monostable multivibrator is adjusted using preset VR1 or VR2 and capacitor C1. For 40kmph limit the time period is set for 9 seconds using preset VR1, while for 60kmph limit the time period is set for 6 seconds using preset VR2. Slide switch S1 is used to select the time period as per the speed limit (40 kmph and 60 kmph, respectively). The junction of LDR1 and resistor R1 is coupled to pin 2 of IC1.
Normally, light from the laser keeps falling on the LDR sensor continuously and thus the LDR offers a low resistance and pin 2 of IC1 is high. Whenever light falling on the LDR is interrupted by any vehicle, the LDR resistance goes high and hence pin 2 of IC1 goes low to trigger the monostable. As a result, output pin 3 goes high for the preset period (9 or 6 seconds) and LED1 glows to indicate it. Reset pin 4 is controlled by the output of NAND gate N3 at power-on or whenever reset switch S2 is pushed.
For IC2, the monostable is triggered in the same way as IC1 when the vehicle intersects the laser beam incident on LDR2 to generate a small pulse for stopping the count and for use in the speed detection. LED2 glows for the duration for which pin 3 of IC2 is high.
The outputs of IC1 and IC2 are fed to input pins 2 and 1 of NAND gate N1, respectively. When the outputs of IC1 and IC2 go high simultaneously (meaning that the vehicle has crossed the preset speed limit), output pin 3 of gate N1 goes low to trigger monostable timer IC3. The output of IC3 is used for driving piezobuzzer PZ1, which alerts the operator of speed-limit violation. Resistor R9 and capacitor C5 decide the time period for which the piezobuzzer sounds.
The output of IC1 triggers the bistable (IC4) through gate N2 at the leading edge of the count-start pulse. When pin 2 of IC4 goes low, the high output at its pin 3 enables astable clock generator IC5. Since the count-stop pulse output of IC2 is connected to pin 6 of IC4 via diode D1, it resets clock generator IC5. IC5 can also be reset via diode D2 at power-on as well as when reset switch S2 is pressed.
IC5 is configured as an astable multivibrator whose time period is decided by preset VR3, resistor R12 and capacitor C10. Using preset VR1, the frequency of the astable multivibrator is set as 100 Hz. The output of IC5 is fed to clock pin 1 of decade counter/7-segment decoder IC6 CD4026.