The architecture enables ultra-narrow 2D semiconductor channels to retain high speed, low leakage and strong current, paving the way for denser, more efficient next-generation electronic chips.
Researchers at Stanford University have developed an innovative transistor architecture that could help overcome one of the biggest challenges facing next-generation semiconductor scaling. By introducing a dog-bone-shaped design for ultra-thin 2D semiconductor nanoribbons, the team demonstrated that transistor channels can be significantly narrowed without sacrificing electrical performance, marking an important milestone for future chip technologies. The findings were published in Nature Nanotechnology.
As the semiconductor industry continues to push transistor dimensions toward atomic limits, two-dimensional (2D) materials such as molybdenum disulfide (MoS₂), tungsten disulfide (WS₂) and tungsten diselenide (WSe₂) have emerged as promising alternatives to conventional silicon. While these atomically thin materials offer excellent electrostatic control, shrinking their channel width has traditionally introduced fabrication defects and degraded device performance.
To address this challenge, the Stanford researchers patterned the semiconductor into a dog-bone geometry, where wider ends anchor metal contacts while the narrow central region forms the transistor channel. The approach minimizes nanoribbon delamination during fabrication and enables reliable production of channels as narrow as about 25 nanometers. The team also adopted a two-step etching process that creates cleaner channel edges than conventional single-step fabrication, further improving device quality.
Electrical testing showed that the ultra-narrow transistors maintained strong switching characteristics across all three 2D semiconductor materials. The devices achieved on-state currents of 560 µA/µm for MoS₂, 420 µA/µm for WS₂ and 130 µA/µm for WSe₂. Notably, the WS₂ devices delivered nearly 100 times higher current density than previous nanoribbon transistor demonstrations using similar materials, while narrow channels did not exhibit increased off-state leakage, a key requirement for low-power electronics.
The researchers believe the work demonstrates that transistor width scaling in 2D semiconductors is more practical than previously thought. Future research will focus on reducing operating voltages to 0.5 V, refining edge quality, shrinking contact dimensions and exploring transistor behavior below the 10-nanometer channel width threshold. Success in these areas could position 2D nanoribbon transistors as viable candidates for replacing silicon nanosheet devices in future generations of high-performance, energy-efficient integrated circuits.
