Friday, May 17, 2024

Multiple Stacked Circuits for More Efficient AI-Based Machine Learning

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The design proposes a highly effective methodology for storing large amount of data as well as maintaining enhanced energy efficiency standards during machine learning

An integrated 3D-circuit architecture for AI applications with spiraling stacks of memory modules. (Image credit:

Machine learning enables computers to be trained using examples/instances for making better and precise predictions regarding an outcome. All this is possible thanks to artificial intelligence (AI). However, AI tends to require a great deal of electrical energy for this purpose (that is training), which raises concerns about its effect on the growing climate change.

To provide a solution to this problem by creating future energy-efficient AI devices, researchers from the Institute of Industrial Science at The University of Tokyo have designed and built a specialised computer hardware, which consists of stacks of memory modules arranged in a 3D-spiral for AI applications.

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Now, scientists from the Institute of Industrial Science at The University of Tokyo have developed

In this novel design where resistive random-access memory modules are stacked with an oxide semiconductor (IGZO) access transistor in a three-dimensional spiral, having on-chip nonvolatile memory placed close to the processors makes the machine learning training process much faster and more energy-efficient. This is because electrical signals now get to travel a much shorter distance as compared with conventional computer hardware. Since training the algorithm (with the help of machine learning) often requires many operations to be run in parallel at the same time, stacking multiple layers of circuits as close as possible to each other is a logical step.

“For these applications, each layer’s output is typically connected to the next layer’s input. Our architecture greatly reduces the need for interconnecting wiring,” says research member Jixuan Wu.

Advancing the efficiency even further

In order to make the device even more energy-efficient, the team implemented a system of binarised neural networks. Instead of having the parameters to be any number, they are simply restricted to be either +1 or -1. This greatly simplifies not just the use of the hardware but also compresses the amount of data for storage.

The device was tested by the scientists for interpreting a database of handwritten digits. The result showed that by increasing the size of each circuit layer, one could enhance the accuracy of the algorithm, up to a maximum of around 90 per cent.

“In order to keep energy consumption low as AI becomes increasingly integrated into daily life, we need more specialized hardware to handle these tasks efficiently,” said research member Masaharu Kobayashi.

With such great development for the decision-making process led by AI, this work is a remarkable step towards equipping smart devices with an advanced internet of things (IoT) technology.


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