Thursday, June 13, 2024

Intel Quartus Prime Upgraded

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Interactive schematic visualisation of unaltered view of RTL design is now available.

Intel Corporation, semiconductor chip designer and manufacturer, announces an updated version of its field programmable gate array (FPGA) design software, Intel Quartus Prime Software version 23.3. This release is expected to add performance and features that make design easier.

The design netlist infrastructure (DNI) is introduced as the primary flow. This provides features like register transfer logic (RTL) analyzer for reviewing RTL netlists, synopsys design constraint (SDC) on RTL which permits the formulation of SDC constraints using RTL net names and early timing analyzer which gives a post-synthesis timing estimate.

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The RTL analyser includes sweep hints viewer to view top reasons for objects to be swept away, object constraints viewer to view objects related to a constraint and object set console providing easier way to view objects.

The company claims that there have been enhancements in quality of results (QoR) for Intel Agilex 7 FPGAs. Observations indicate a noticeable increase in fabric performance (average 50%) and a reduction in total power consumption (up to 40%) in comparison to the previous generation of Intel FPGAs. Input/output buffer information specification (IBIS) writer for Agilex is included. 

A simulator for the Intel Agilex 5 E-Series hard processor system is introduced. There are enhancements in IP, featuring new IP subsystem examples for ethernet and memory. Parameterisable macros for IOPLL IP and clock domain checking (CDC) IP are included. Compilation quality is expected to be improved.

The Nios V/c compact microcontroller core utilizes the RISC-V RV32I instruction set architecture. There is a Nios V configurable example design that is compatible with the Agilex 7 F-Series FPGA development kit.


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