The open-source TinyGPU v2.0 packs around 240,000 transistors and has been verified as a working ASIC, rendering 3D graphics at up to 15 frames per second.
An open-source graphics processor with around 240,000 transistors has successfully moved from FPGA testing to fabricated silicon. TinyGPU v2.0, developed by Pongsagon Vichit, was produced through the Tiny Tapeout SKY25b shuttle and has demonstrated real-time 3D graphics on the fabricated ASIC. The GPU supports up to 1,000 triangles, transformation and lighting, rasterisation, backface culling, flat shading and affine texture mapping.
The finished chip was tested using interactive 3D scenes controlled through a gamepad. Demonstrations include a low-polygon model being manipulated in real time and a rotating, zooming Earth globe. The tests confirm that the TinyGPU v2.0 graphics pipeline operates on physical silicon, although its performance remains broadly similar to the earlier FPGA implementation.
TinyGPU v2.0 operates at around 25 MHz and renders at 320 × 240 pixels with 4-bit colour, supporting up to 16 simultaneous colours. The design uses a 4-bit double buffer and an 8-bit depth buffer, with both stored in external QSPI RAM. Earlier Basys3 FPGA testing achieved between 7.5 and 15 frames per second, depending on the scene. A 1,000-triangle scene runs at around 6.5 frames per second, while the fabricated ASIC is not expected to significantly outperform the FPGA implementation.
The graphics processor uses a fixed-function pipeline rather than the programmable shader architecture found in modern GPUs. Its open-source hardware is available through the project’s GitHub repository and is implemented primarily in Verilog. TinyGPU demonstrates how a relatively complex graphics pipeline can be taken from an open hardware design through FPGA validation and into fabricated silicon using a shared ASIC manufacturing platform.
Development is continuing with TinyGPU v3.0, which is planned to add a programmable pixel shader. The design is inspired by DirectX 8 Pixel Shader 1.1 and is expected to support four-pixel SIMD execution, up to 31 instructions per shader, a 26-operation instruction set, masked branching and four 8-bit temporary registers. The next version is currently expected around December 2026 or January 2027.
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