Testing High-Speed Memories

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Some of the other tests performed are:
Address lines test. It tests the functionality and connection of address lines. The memory is initialised with all 1’s, after which a ‘0’ is written to all the bits of the address. One of the lines is then changed to ‘1’ and using a high-speed digital I/O board (HSDIO), all the lines are read back. The expected value is all 1’s. This test is then repeated for all address lines.
Data lines test. In this test, each bit of memory is tested to see whether it can store and return correct values. Once again, all the bits are initialised to ‘1.’ The first bit of an address is changed to ‘0.’ Using the HSDIO board, the bit is acquired and verified as a ‘0.’ This test is then rotated through each bit of the address and repeated for all memory locations.
Self address test. This test writes the value of its own address to each location. Using an HSDIO board, each address is read and checked for values of the data stored. This test is then repeated several times.
Moving inversion one’s. In this test, an all 1’s moving algorithm is written to the memory and read back. The memory is initialised to all 1’s. It is then filled with all 0’s from top to bottom verifying each location. The HSDIO board is used to verify the locations. Then the memory is filled with all 1’s. The values are read back using the HSDIO board and all the data is verified.
Random moving inversion. Similar to moving inversion one’s test, in this test the memory is tested with a moving inversions algorithm using random data. The memory is initialised to all 1’s. Random values are written to the memory, from top to bottom, and then verified.
Random number sequence. In this test, random values are written to and read from the memory. This procedure is repeated for several locations.

—Information provided by Abhay Samanth of NI

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Al Crouch, chief technologist at ASSET InterTech, explains in his whitepaper, “During design and new product introduction, testing memory in a timely fashion is particularly critical if the new system is to be delivered promptly to the marketplace. During the initial phase of board bring-up when first prototypes are received, memory tests are performed to identify the root causes of failures or faults in the design of the memory architecture so that these can be quickly corrected prior to the design’s release to production. Meanwhile, performance of the memory architecture is characterised to determine whether the design meets or exceeds its performance specifications.”

Bhatia says, “The JEDEC specification requires compliance at the hard-to-reach fine ball-grid array (FBGA) package ballout on the dynamic random-access memory (DRAM) chip. Due to difficulty in probing at BGA pins, engineers tend to probe at other locations such as the signal trace or surface-mount components like termination resistors and capacitors. Although this may seem straightforward, signal integrity could be compromised by probing here. First, probing at these locations often causes signal reflection, resulting in non-monotonic edges, overshoot, ringing and other issues. Rather than true signal performance, you see a signal that includes the effect of reflection at components. This can cause errors on slew-rate and setup and hold-time measurements.”

“To address this probing challenge and to optimise DDR probing, Agilent has designed specialised tools. One such tool is BGA probe adaptor—a thin fixture that can be attached between the DRAM chip and the circuit board with a compatible footprint on the top and bottom side. The signals at the DRAM ballout are then routed to the top side of the BGA probe adaptor, so the oscilloscope and logic analyser probes can access them. This method provides a direct signal access point to the DRAM ballout for true compliance with the DDR specification. Since it’s compatible with oscilloscopes and logic analysers, you can perform parametric and functional measurements with the same BGA probe,” he adds.

According to Chestnut, “Compared to other electrical serial data physical-layer validation requirements, the bandwidth required for DDR is not very high. Oscilloscopes in this bandwidth range are widely available. However, DDR is a parallel data bus with many data lines—up to 64 data lines are not uncommon. As speeds increase, the need to perform electrical physical-layer validation on all of the data lines, and not just the assumed ‘worst case’ data lines, will increase. Separating the read and write data signals properly to perform validation requires at least two and often three other signals, leaving a conventional four-channel oscilloscope capable of validating only one data line at a time.”

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