Researchers have demonstrated a ferroelectric memory chip that performs both random sampling and AI computation, paving the way for compact, energy-efficient generative AI hardware for future edge and embedded electronics.
A research team at Seoul National University has unveiled a ferroelectric memory-based semiconductor that combines two of generative AI’s most critical functions—random sampling and deterministic computing—within a single chip. The breakthrough could significantly reduce the size, power consumption and complexity of future AI accelerators by eliminating the need for separate hardware blocks dedicated to these operations.
Generative AI models differ from conventional AI because they require both mathematical computation and controlled randomness to generate new content such as images, videos and synthetic data. Existing hardware typically performs these tasks using separate circuits or software modules, increasing silicon area, latency and energy usage. The newly developed architecture integrates both capabilities into one ferroelectric memory array, offering a more compact hardware solution.
The innovation relies on hafnium oxide (HfO₂)-based ferroelectric memory, a non-volatile memory technology compatible with standard CMOS semiconductor manufacturing. Researchers exploited the voltage-dependent behavior of the memory cells to switch between two operating modes. At higher voltages, the device produces random telegraph noise (RTN), generating the stochastic values required for latent-space sampling in generative AI models. At lower voltages, the same cells suppress the noise and perform stable vector-matrix multiplication (VMM), the core computational operation used in neural network inference.
To validate the concept, the team fabricated a NOR-type ferroelectric memory array on a 6-inch wafer and integrated it into a hardware implementation of a variational autoencoder (VAE). By optimizing voltage levels and sampling duration, the chip successfully generated facial images from the CelebA dataset while demonstrating both probabilistic sampling and deterministic computation on the same hardware platform.
Beyond image generation, the technology could accelerate the development of low-power edge AI processors, neuromorphic computing systems and on-device generative AI applications where energy efficiency and silicon area are critical. Because ferroelectric memory is compatible with existing semiconductor fabrication processes, the architecture offers a practical route toward large-scale commercial deployment. Researchers now plan to improve sampling speed, increase memory array size, enhance parallel processing and optimize peripheral circuitry to enable real-time generative AI hardware.
