A 0.7 nm semiconductor chip packs nearly 100 billion transistors and introduces a transistor design that pushes chip scaling beyond the 1 nm barrier.
IBM has introduced what it says is the world’s first sub-1 nanometer (nm) semiconductor technology, built on a transistor architecture at the 0.7 nm (7 angstrom) process node. The breakthrough comes as the semiconductor industry approaches the physical limits of conventional transistor scaling. Semiconductor chips are used across computing, communication devices, consumer electronics, transportation systems, industrial equipment, and critical infrastructure.
The sub-1 nm chip integrates nearly 100 billion transistors on a chip about the size of a fingernail, almost doubling the transistor density of IBM’s 2 nm chip introduced in 2021. The achievement combines several structural and material changes, including IBM’s three-dimensional nanostack architecture, to improve chip performance and energy efficiency as transistor dimensions approach the atomic scale.
According to IBM, the technology could deliver up to 50% higher performance or 70% better energy efficiency than its 2 nm chips. These improvements could benefit applications such as generative AI, cloud computing, and electronic systems.
At the center of the breakthrough is IBM’s “nanostack” transistor architecture, described as the industry’s first three-dimensional nanosheet-based transistor design. Unlike existing nanosheet technology, the nanostack architecture vertically stacks and staggers transistors using 3D sequential integration, allowing more transistors to fit within the same chip area. The design also enables different material combinations to be used in each stacked layer, allowing individual transistors to be optimized for performance and power consumption.
IBM validated the architecture through ultra-thin dielectric bonding in CMOS integration, dual-channel engineering, and functional CMOS inverter operation with the expected switching characteristics. These demonstrations confirmed that the nanostack design can be fabricated and perform computational tasks.
The development extends logic scaling below the 1 nm node, moving semiconductor manufacturing into the angstrom-scale era, where device dimensions approach the size of individual atoms. Although process nodes no longer represent exact physical dimensions, IBM’s 0.7 nm (7 angstrom) technology shows that transistor scaling can continue beyond current limits. The company expects the nanostack architecture to support another decade of semiconductor scaling.
