An AI-powered verification solution automatically transforms chip specifications into executable test suites, helping engineers reduce manual effort while accelerating functional verification of complex SoCs.
Breker Verification Systems has launched an AI-driven SoC verification solution by integrating its Trek Test Suite Synthesis platform with Moores Lab AI VerifAgent. The product is designed to automate one of the most time-consuming stages of chip development by converting written SoC specifications into executable verification tests, enabling engineers to accelerate functional verification while improving coverage across simulation and emulation platforms.
The key features are:
- Generates verification tests directly from written SoC specifications
- Produces executable C and SystemVerilog test programs
- Supports simulation and hardware emulation environments
- Compatible with multicore and TLM-based verification flows
- Uses agentic AI to automate verification planning and scenario creation
The solution combines Breker’s portable stimulus technology with agentic AI to automate specification analysis and test generation. Instead of manually creating verification plans and writing test scenarios, engineers can use the platform to interpret functional specifications and automatically generate verification content for increasingly complex multicore and heterogeneous SoC designs.
The AI-driven workflow analyses design specifications, creates scenario models, and feeds them into the Trek Test Suite Synthesis engine to produce executable C and SystemVerilog test programs. These tests can run across simulation and emulation environments, enabling broader reuse of verification content throughout the chip development cycle.
Designed for modern semiconductor development, the solution supports multicore architectures, transaction-level modelling (TLM), and heterogeneous verification environments. It enables verification teams to validate hardware-software interactions, complex processor subsystems, and system-level functionality while reducing the manual effort typically associated with verification planning and scenario development.
The platform is intended for developers of AI accelerators, automotive processors, networking chips, data centre SoCs, consumer electronics, and other advanced semiconductor devices that require extensive functional verification before tape-out. By automating specification-to-test generation, it aims to shorten verification cycles, improve productivity, and help engineering teams achieve higher functional coverage.
The AI-powered verification solution also enables reusable verification scenarios across multiple verification platforms, allowing generated tests to be deployed consistently throughout the verification flow. This helps design teams streamline validation processes while supporting increasingly complex silicon designs.
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