Single-crystalline cobalt silicide becomes more conductive as it thins, reaching one-tenth of copper’s resistivity at 20 nanometres and powering a 16-nanometre-node ring oscillator.
A team led by researchers at The Hong Kong Polytechnic University has demonstrated single-crystalline cobalt silicide (CoSi) as a potential on-chip interconnect material. The researchers report that a 20-nanometre-thick CoSi film achieved a resistivity around one-tenth that of copper at the same thickness.
Interconnects, rather than transistors alone, have become an increasingly important limitation in advanced semiconductor nodes. As copper wires become narrower, electron scattering from surfaces and grain boundaries increases their electrical resistance. This phenomenon, known as the resistivity size effect, becomes more severe as interconnect dimensions continue to shrink, increasing power loss and making signal transmission more difficult.
CoSi is a topological chiral semimetal, and the researchers report an unusual thickness-dependent behaviour. As the film becomes thinner, its resistivity falls rather than rising. According to the paper, electrical conduction increasingly shifts towards a highly conductive surface channel associated with Fermi-arc surface states, reducing the influence of bulk scattering. This is the opposite of what happens in copper interconnects, where shrinking dimensions increase electron scattering and therefore raise resistivity.
At a thickness of one micrometre, the CoSi film has a reported resistivity of 7.0 microohm-centimetres. When thinned to around 20 nanometres, this falls to 0.72 microohm-centimetres. The material also sustains current densities of up to 100 million amperes per square centimetre and operates at temperatures up to 450 degrees Celsius. The reported cohesive energy of 5.4 electronvolts and migration barrier of 3.7 electronvolts are relevant to material stability and resistance to electromigration rather than switching speed. The researchers also report that the films remain suitable for radio-frequency operation up to 40 gigahertz.
Copper interconnects typically require diffusion barriers and liner layers to prevent copper atoms from migrating into surrounding materials. These layers become increasingly difficult to scale as interconnect dimensions shrink because they occupy a growing proportion of the available cross-section while contributing little or nothing to electrical conduction.
CoSi’s reported migration barrier and cohesive energy suggest strong atomic stability and potential resistance to electromigration. This could reduce the materials and integration requirements associated with conventional copper interconnect stacks. However, the result should not be interpreted as demonstrating barrier-free semiconductor integration unless that capability is explicitly demonstrated. Whether CoSi can eliminate diffusion barriers entirely, or simply reduce barrier requirements, would depend on its behaviour with surrounding dielectric and semiconductor materials in a complete fabrication process.
This is a laboratory demonstration with a meaningful integration step behind it. The team incorporated CoSi interconnects into a 16-nanometre-node silicon ring oscillator and reported operation at the same frequency as a comparable conventionally metal-interconnected version. Matching the existing circuit’s performance is a useful validation of the material and integration approach, but it is not a performance advantage.
The larger manufacturing challenge remains unresolved. Growing single-crystalline CoSi reliably at wafer scale, across complex chip topography and within the thermal budget available for back-end-of-line processing would require further development. The reported work is therefore far from a production-ready semiconductor manufacturing process.
India’s semiconductor manufacturing programme is currently focused largely on mature and established process technologies, where copper interconnect scaling is less likely to be the immediate bottleneck. The significance of this research for India therefore lies less in near-term domestic fabrication and more in the efficiency and performance of advanced chips that India will continue to design, import and deploy.
Interconnect resistance contributes to power loss in advanced processors and AI accelerators, making lower-resistance interconnect materials potentially relevant to the energy efficiency of future high-performance computing systems. This could matter for data centres, where electricity is a major operating expense, although the benefits of CoSi would need to be demonstrated in production-scale advanced chips before any direct impact on data-centre power consumption could be claimed.
The reported radio-frequency operation up to 40 gigahertz also makes the material potentially relevant to high-frequency electronics research. Indian organisations including SAMEER and DRDO laboratories work on advanced microwave and radio-frequency technologies, where interconnect losses can become an important design consideration. However, applying this laboratory CoSi technology to indigenous high-frequency devices would require substantial further work on fabrication and integration.
Copper has carried signals across integrated circuits since the late 1990s, and replacing it has proved exceptionally difficult. A credible alternative that improves rather than loses conductivity as dimensions shrink is therefore worth watching, even if practical semiconductor manufacturing remains years away.
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