This role involves deep, hands-on technical work in a small, collaborative environment.
- Design FPGA based acceleration using HLS/Verilog/VHDL
- Develop system level specification and architecture
- Develop system level register specification and programming model
- Develop module level specification and micro-architecture
- Perform Floor planning, Physical optimization, Static Timing analysis, and timing closure
- Debug, root cause analysis & troubleshooting of complex FPGA design at full system level in the Alveo or custom platform
- A minimum of Bachelors in EE/ECE with 5+ years of relevant work experience.
- Strong programming experience in C/C++ is required.
- Experience in building fpga based systems using hls/c++/opencl/verilog/system verilog
- Experience in running, debugging and profiling programs on real HW board (embedded debug) is a big advantage.
- great design, problem solving, and data analysis skills, with demonstrated passion for quality, performance, and engineering excellence
- Experience in doing performance profiling of application, functional and memory debugging is required.
- Must have basic experience in of the scripting language like shell script, perl or python.
- Must have experience in Linux based development and debug.
- General awareness of ASIC or FPGA design flow including synthesis, place and route is a big advantage.
- Be able to excel in team environment.
- Demonstrated ability to identified technical problem, propose viable solutions, and apply technical solutions.
- experience in running latest xilinx/intel fpga tools is a bigplus
- hands on with lab fpga debug tools (jtag,signaltap/chipscope/logicanalyzer) is a bigplus
- knowledgeable in one or more industry standard interfaces such as amba axi, altera avalon, pcie, hbm, and ddr4 is preferred
- thorough understanding of digital logic design concepts, and multiple clock domain designs
- good understanding of x86 architecture and dma concepts
- good communication skills
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