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Location: Ahmedabad
Company: Pronesis Technologies
The Physical Design Engineer will perform block-level and full-chip implementation tasks, including floorplanning, placement, clock tree synthesis, routing, and timing closure for ASIC/SoC designs. Responsibilities include power, performance, and area optimisation, working on constraint development, and resolving physical verification issues such as DRC, LVS, and antenna violations. The role involves close collaboration with front-end design, verification, and test teams to ensure design integrity, sign-off readiness, and successful tape-out. The engineer will also support documentation, participate in design reviews, and contribute to continuous improvement of physical design flows and methodologies.
Qualifications
- Strong foundation in ASIC/VLSI concepts, digital design, and SoC implementation methodologies.
- Hands-on experience with physical design flows, including floorplanning, placement, CTS, routing, and timing closure using industry-standard EDA tools.
- Knowledge of static timing analysis, signal integrity, power integrity, and low-power design techniques.
- Experience with physical verification (DRC, LVS, ERC) and familiarity with foundry design rules and technology files.
- Lead end-to-end physical design implementation from Netlist to GDSII.
- Own timing closure, Static Timing Analysis (STA), and optimisation of setup and hold violations.
- Optimise Power, Performance, and Area (PPA) to meet design targets and project milestones.
- Analyse and resolve signal integrity, crosstalk, congestion, IR drop, and electromigration (EM) issues.
- Perform physical verification, including Design Rule Checking (DRC) and Layout Versus Schematic (LVS) coordination.
- Debug complex physical design challenges and implement effective optimisation strategies.
- Collaborate with RTL, synthesis, DFT, STA, and sign-off teams to ensure smooth design integration.
- Drive design quality, methodology improvements, and execution within project timelines.
- Provide technical guidance and mentorship to junior engineers.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or a related field.
