Tuesday, June 18, 2024

Silicon Design Engineer at AMD

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Location: Bangalore

Company: AMD

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CPU verification engineer

The AMD Cores design & verification group develops high-end, next-generation CPU’s that power different AMD SoC which is eventually set to change the course of how computing is visualized. The engineering teams are distributed across US and India. The CPU verification team in India is one of AMD India’s first teams & involved in contributing to the tape out of numerous AMD systems. As part of the CPU Design Verification team, our team will be responsible for the maintainability & scalability of the RTL & testbench environment that is used for the development & verification of the design. As always, the team is dedicated to coming up with innovative solutions to overcome new challenges related to specific project requirements and time-to-market.

Key Responsibilities

  • Will work with different stakeholders in getting a thorough understanding of high-level feature/s & get clarification(if any).
  • After feature understanding, populate a high-level test plan that details how we plan(Stimulus, debug, coverage) to verify the feature & what we cover/don’t cover as a part of the feature verification. Get it reviewed & incorporate feedback.
  • Develop directed/random test cases to target the feature bring up. Debug fails(debug needs an understanding of computer architecture, micro-architecture & TB environment), file RTL/Verify bugs, and fix testbench issues.
  • Ensure feature health is stable & in parallel work on evaluating stimulus coverage. If needed, tweak/add stimulus as appropriate.
  • If the feature demands, then develop SV checker & SV cover points. All this while learning & understanding uarch is an integral part.
  • On a need basis, work on Post-Si bug recreation.

Skills and Experience Requirements:

  • B.E/B.Tech/M.E/M.Tech in Computer Science/Electrical/Electronic Engineering.
  • 3+ years of experience in CPU verification.
  • Good understanding of basics of computer architecture & digital systems.
  • Good understanding of Verilog, System Verilog, and C++. Some knowledge of shell/Perl scripting is a plus.
  • Understanding of assembly(x86) code.
  • Understanding of Formal Verification methodology (with tools VSI-FV/JASPER/IFV/IEV) is a plus.
  • Should be a good team player, quick thinker, pro-active, adaptable & outspoken/approachable.
  • Must be well-organized and should be able to multitask well with due diligence on closing his/her tasks.


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