Researchers develop a new magnetic tunnel junction quad technology for better endurance and reliable data retention.
The DRAM technology is scaling faster, resulting in high leakage power, worse data retention time behavior, and large process variations.
Researchers from Tohoku University have developed a new magnetic tunnel junction (MTJ) quad-technology that provides better endurance and reliable data retention—over 10 years—beyond the 1X nm generation. The technology meets the requirement of X nm CMOS technology, which has a potential to enable ultra-low-power consumption for Internet of Things (IoT) edge-devices in mobile communication, the automotive industry, consumer electronics, and industrial/infrastructure equipment.
The research was presented at the 2021 Symposia on VLSI Technology and Circuits. Many logic circuits implement spin transfer-torque magnetoresistive random access memory (STT-MRAM) as a low power consumption technology. But fabrication with 1X nm design rules is difficult.
The newly developed Quad-interface MTJ (Quad MTJ) technology has three new technologies: a low RA technology, a low damping material in the recording layer, and a stable reference layer.
This enabled it to have (1) better retention characteristics of over 10 years, (2) endurance that exceeded at least 6 X 1011, (3) a high-speed write operation of 10 nanoseconds, (4) a low power consumption operation of 20%, and (5) a low write error rate combined with a circular diameter of 18 nm.
Researchers believe that the applications of this technology can expand to the leading-edge logic, achieving ultra-power consumption, excellent scalability and high reliability in application processors.