Wednesday, February 21, 2024

Post-Silicon Testing

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Concurrent testing is an effective method to drive the test times. This can be accomplished by testing different cells of the same silicon in parallel, i.e., testing multiple cells at the same time wherever possible. As the SoC is a combination of various digital cores like ADCs, DACs and digital and analogue cells, all of these can be tested in parallel and then the entire device tested for functionality. This will reduce the overall time significantly.
[stextbox id=”info” caption=”Some semiconductor test equipment providers”]
• Agilent
• Qmax
• Terradyne
• Keithley
• Amkor
• Verigy[/stextbox]

“Another test strategy offered by ATE manufacturers is parallel multi-site testing where multiple devices can be tested simultaneously (at more than 128 sites), reducing the overall test time and increasing throughput significantly,” comments V.K Rajiv, product manager, Qmax.

Many semiconductor manufacturers like Intel and TI have home-grown ATEs built using in-house tools. They have their own test programs, and only the conversion tools are provided by EDA vendors.

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Veerappan explains, “There is no common test program which can test all the chips. You need to customise the program to your chip. Test engineers have to develop the right skills to write efficient test programs.”

Rajiv adds, “Many ATE manufacturers now provide test program development software that are fully graphical user interface based and also automate many development procedures to facilitate faster test program development and minimise programming errors.”

Design of the load board is another critical area. Veerappan shares, “It has to have all the precautions inbuilt. For example, in case of high voltage, it should have a high-voltage cut-off. All types of arrangements are made in the circuit of the load board.”

Test program reuse can significantly reduce the cost and time of testing. Veerappan says, “Reuse is a smart way of reducing time. Currently, 30-40 per cent of the test programs, boards and tools can be reused. Learning of the reuse technique saves a lot of time spent in re-inventing a wheel. It reduces the time-to-market.”

“With rapidly evolving semiconductor technologies, chips go from introduction to obsolescence in less than three years. Obviously, time-to-market and manufacturing cost of new products are extremely important to the company’s bottom line, and one key element that drives both these factors is semiconductor testing. ATE manufacturers need to ensure that the existing ATEs are highly scalable and adaptable to the rapidly changing semiconductor industry,” adds Rajiv.

Ultimate goal: minimise cost and time, maximise yield
The operating speed of ICs has increased greatly. The test systems should be able to match the speed of these faster chips. Another area of development is the manufacturing process technology. As manufacturing moves from 90nm to 65nm process, the tester should be capable of handling the lower footprint and producing reliable test results.

Process technology changes have also had serious effect on the cost of test and the need for test. Kumar adds, “With 32nm technology becoming a reality in 2010, test challenges have only increased. Sub-pico-Farad capacitance measurements and tens of atto-ampere (current) measurements have become essential.”

Today, chips have become very complex incorporating about four million gates. The ATE should be able to test these chips in minimum possible time. You could spend 20 minutes or five seconds to test a chip and every second adds to the cost of chip production. The ultimate goal of any chip manufacturer is to be able to test all the chips in minimal time. This will reduce the cost and increase the yield.

The author is a senior technology journalist at EFY


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