Wednesday, December 7, 2022

“The next five years are expected to see more technology inflections and shifts than the past 15 years”

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Q: What were the challenges faced while moving to single wafer technology?
As with any major cross-industry shift, there were indeed many challenges. A major aspect was to ensure tool readiness that is exactly in sync with the customer’s technology roadmap. Tuning a company’s long-term R&D effort to be perfectly timed with a major inflection is, in itself, a major challenge. So one can only imagine engaging the entire equipment supply chain in a highly collaborative R&D effort to work towards the new tool standard. We needed to actively manage the risk of the migration to a newer industry standard on multiple fronts, such as technology, architectural changes like wafer handling systems, and financial R&D planning, etc.

But more than any other factor, ensuring the availability of a solution that provided a significant improvement in on-wafer performance, with a low risk, was essential to get customers to adopt the new single-wafer standard on a significant scale.

You did your Ph.D on ‘In-situ Integrated Rapid Thermal Processing (RTP) of Advanced Materials and Devices.’ How has the adoption of RTP technology in dynamic random access memory (DRAM) integrated circuits helped today’s electronics industry?

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What the adoption of RTP has enabled is, basically, scaling of DRAMs below the 0.6-micron technology node. Today, the industry is scaling to the 25nm node. Once proven in DRAM manufacturing, RTP was adopted in the manufacture of other devices such as logic, non-volatile memory, analogue and MEMS. Today, single RTP is a fundamental enabling technology in the fabrication of the most advanced semiconductor devices.

Q: Could you give us an insight into the emerging technologies in the semiconductor industry?
The next five years are expected to see more technology inflections and shifts than the past 15 years. A major inflection starting to play out now is the fundamental shift to 3D device architectures—such as finFET in the logic space and 3D NAND in Flash memory. Realising these complex structures requires more process steps, to selectively deposit or remove material with highly repeatable precision in a volume manufacturing environment.

In the longer term, we can expect to see the 450mm inflection, during which the wafer-size standard moves from a 300mm (12-inch) diameter to 450 mm (18-inch). We are currently doing R&D to develop tools for the 450mm wafer standard.

Q: Silicon is almost always used in designing and manufacturing ICs. Is there any research being done on an alternate material?
As mentioned, tools have evolved to selectively deposit or remove a wide variety of materials previously unknown to semiconductor processing, with very high levels of precision.

In terms of the substrate itself, there is quite a lot of fundamental research going on in academia. A good example is the use of graphene as a basic substrate material. There are also certain process steps in packaging schemes (such as interposers), where glass can be considered as an alternative to silicon.

Nevertheless, the well understood electrical and physical properties of silicon handling, and the economics of processing it, make us believe that silicon is to remain the mainstay substrate material of choice for quite some years to come.

Q: Congratulations on your recent achievement on becoming an IEEE Fellow. Would you like to share your thoughts on that?
It is certainly a prestigious honour and I am very humbled to receive it. I consider it as one of the highlights of my career, and I am pleased to have been able to make a meaningful contribution to the industry. It is gratifying to know that my work on the development and implementation of single-wafer RTP technology has led to key improvements in device performance and manufacturing cycle times.


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