Can sparse neural networks make edge AI faster without increasing power consumption? An FPGA toolkit aims to prove they can.
Microchip Technology has introduced VectorBlox 3.0, an updated software development kit (SDK) designed to simplify the deployment of convolutional neural network (CNN) models on PolarFire FPGAs and SoCs. The free toolkit integrates optimisation, compilation and deployment into a single workflow, enabling developers to accelerate FPGA-based AI implementation while reducing development time for edge applications.
The release targets AI inference in power-constrained and mission-critical environments, including aerospace, defence and industrial systems, where balancing performance, power efficiency and reliability is essential. By supporting multiple AI workloads on a single FPGA, the SDK enables developers to consolidate vision- and sensor-based AI functions onto one low-power device, reducing hardware complexity while improving system efficiency.
A key addition in VectorBlox 3.0 is support for sparse neural networks, allowing the accelerator to skip zero-valued operations during inference. The sparsity-based model compression technology, reduces compute and memory requirements while maintaining model accuracy. According to the company, this improves inference performance and lowers power consumption, making the platform suitable for always-on edge AI deployments. The SDK integrates with the CoreVectorBlox IP and is supported by the Libero SoC Design Suite.
The announcement also highlights applications beyond terrestrial systems. The platform supports Spacecraft Pose Network v2 (SPNv2), a vision-based neural network for spacecraft position and orientation estimation used in autonomous rendezvous, docking, satellite inspection and space debris removal. Built on PolarFire FPGAs and SoCs, the solution combines secure boot, anti-tamper protection and single-event upset immunity for operation in harsh environments.
“As AI models continue to grow in complexity, compression is becoming essential for deploying intelligence at the edge,” says Shakeel Peera, Corporate Vice President and General Manager, FPGA Business Unit at Microchip Technology. “With VectorBlox 3.0, we’re leveraging sparsity-based model compression from our Neuronix acquisition to reduce compute demands while preserving accuracy.”
Click here for the official announcement.
