Sunday, July 14, 2024

JOB: Design Engineering Architech At Cadence In Bengaluru and Noida

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Location: Bengaluru and Noida

Company: Cadence

  • Design and implement DFT IP w/ Verilog/SystemVerilog and/or VHDL
  • Design and implement RTL for DFT IP incl. POST, IST
  • Develop synthesis automation for DFT IP including synthesis and timing constraints, RTL insertion and verification
  • Own and maintain, extend, and enhance existing DFT IP like LBIST

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