APPLY HERE
Location: Bengaluru
Company: Quest Global
Key Responsibilities
- ATPG, Scan 4-8 years
- Should have worked on large SOC’s with low power knowledge
- Should be knowledgeable on Scan and test coverage improvement
- Should have adequate exposure to IEEE1500 and IEEE1687
- Should be knowledgeable on DFT STA modes and be able to support timing closure
- Should be familiar with MBIST ATPG simulations ( both SDF and zero delay)
- Should have adequate ATE knowledge to be able to handle post-silicon debug
- Should be familiar on techniques to contain IR drop in all DFT modes including MBIST and Scan
- Should be knowledgeable on Test cost sensitivity to a project overall cost
- Should have knowledge on running/debugging CLP and LP-LEC issues
- Familiarity with Multi-voltage, multi-power domain based Low power implementation is a plus
