Wednesday, June 12, 2024

HW Engineer DFT at Capgemini

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Location: Bengaluru

Company: Capgemini

Job Description

  • Will be responsible for Designing and Implementing DFT techniques.
  • Should have a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability.
  • Test Modes implementation and verification, scan insertion including on-chip compression.
  • Implementing, integrating, and verifying memory BIST and boundary scan.
  • ATPG Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test  Coverage and simulations at gate level with timing (SDF).
  • Basic understanding of complete SOC design and flow.
  • Cross-functional teams interaction for issue resolution.
  • Participate in driving new DFT methodology and solutions to improve quality, reliability, and system test and debug capability.
  • Hiring candidates with this specific personal characteristic and qualifications.
  • Mentoring junior engineers and driving innovation/automation.
  • Excellent problem-solving and analytical skills.
  • Excellent communication, teamwork, and networking skills.

Primary Skills

  • Should Have a Good understanding of Design and DFT Architecture.
  • Should have been part of at least 3 Tapeout SoC.
  • Well Versed with ATPG Tools & MBIST Tools.

Secondary Skills

  • Team Player, Strong Business Acumen with an understanding of organizational issues (conflict resolution between stakeholders).
  • Familiarity with Desired Flexibility and adaptability with respect to project management.


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