2. Decide location: Most wearable designs do not require board-level ESD diodes at each of the integrated circuits’ pins. The designer should determine which pins have exposure to the outside of the application where user-generated ESD events are likely to occur. If it can be touched by the user, the communication/control line is at risk to become a pathway for ESD to enter the integrated circuit. Typical circuits include button/switch control, audio, USB and other data buses; their pad layouts should be reduced to fit 0201 or 01005 outlines and optimize board space usage.
3. Review length of trace: Several considerations for trace routing should be made to safeguard the integrated circuits’ pins using a ESD diode—from I/O to ground. Unlike lightning transients, ESD does not unleash a large amount of current for a long duration. It is necessary to move the charge from the protected circuit to the ESD reference as quickly as possible to cope with ESD. The length of the trace—from the I/O line to the ESD component and from the ESD component to ground—are the overriding factors, not the width of the trace to ground. To limit parasitic inductance, the length of the trace should be kept as short as possible. This inductance will result in inductive overshoot—a brief voltage spike that can reach hundreds of volts if the stub trace is long enough. Recent package developments include µDFN outlines that fit directly over the data lanes to eliminate the need for stub traces.
4. Examine HBM, Machine Model (MM) and Charged Device Model (CDM) definitions: These test models are used by the semiconductor supplier to characterize the ESD robustness of the integrated circuits that run the portable or wearable device. Most suppliers have excellent in-house ESD policies and reduce the voltage test levels to save die space.
While these strict ESD policies benefit the supplier, the application designer ends up with a chip that is very sensitive to application-level ESD, which must not be allowed to fail due to field-level or user-induced ESD. To succeed, the designer must select a board-level device that is robust enough to protect against intensifying electrical stresses, but with low enough clamping to protect the sensitive integrated circuitry. It is important to consider IEC 61000-4-2 and dynamic resistance when evaluating an ESD protection device.
The rapid growth of the wearable market has made it ever more necessary for design engineers to consider circuit protection and proper board layout practices early in the design process to ensure long-term safety and reliability. ESD diodes are designed to work with small form factors and high levels of ESD robustness to safeguard wearable devices and their users. Key steps to provide ESD circuit protection for wearables include determining the TVS diode configuration, diode location, and length of the trace.
Additionally, decreases in HBM, CDM and MM test voltages are challenging designers to find protection solutions that account for ESD robustness (or lack thereof) of the wearable’s electronics to meet the protection needs of this highly sensitive circuitry. Lastly, at the same time the ESD protection is being considered, overcurrent protection of the charging line and battery should be attacked. Littelfuse has a full line of space efficient surface-mount fuses and Resettable PTCs to protect those circuits.
About the Author
Jim Colby is a manager of semiconductor business development at Littelfuse, Inc. His responsibilities include introducing new products to markets, as well as identifying and developing strategic growth markets. He received his BSEE from Southern Illinois University (Carbondale) and his MBA from Keller Graduate School of Management (Schaumburg). He has been with Littelfuse for over 15 years and has worked in the electronics industry for more than 23 years.