Why Run Gate-Level Simulations?


Gate level simulation targets the maximum desired operating frequency of the design. Some signals that are critical for gate level simulation debug can be preserved during synthesis. A list of all synchroniser flops is generated using CDC tools.

Asynchronous paths where timing checks need to be turned off are analysed and a complete list of such flops is prepared, which also includes reset synchronisers. Timing checks are turned off on all such flops to avoid any redundant debugging, otherwise these will cause X corruption in gate level simulation.

This work should ideally be done before the SDF arrives. It may happen that the names of the synchronisers in RTL and the netlist are different. All such flops should be updated as per the netlist. Also, correct standard cell libraries, correct models of analogue blocks and more should be picked for gate level simulation.

Unit-delay gate level simulation for test bench cleanup setup is done for unit delay gate level simulation and test cases that are planned to be run on gate level are run with this setup to clean the test bench. This is done because unit-delay simulations are relatively faster and all test bench/testcase-related issues can be resolved.

Running unit-delay gate level simulation is recommended because one can catch most of the test bench/testcase issues before the arrival of SDF. After SDF arrives, focus should be more on finding the real design/timing issues. So one must make sure that the time does not get wasted in debugging test-case-related issues at that time.


The challenge in gate level simulation is X propagation debug. X corruption may be caused by a number of reasons such as timing violations, uninitialised memory and non-resettable flops. There generally are uninitialised flops in design which due to the architecture are guaranteed not to cause any problems. There is a need to find out all such flops in the design and initialise these to some random value (either zero or one) so as to mimic silicon. It gives a clear picture of how the design will behave at the desired frequency with actual delays in place.

Although gate level simulation has its own set of challenges like set-up issues and long run time, among others, it is still very much a part of the sign-off process.

V.P. Sampath is an active member of IEEE and Institution of Engineers India Ltd. He is a regular contributor to national newspapers, IEEE-MAS section, and has published international papers in VLSI and networks



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