Three teams have won the Digital India RISC-V Grand Challenge using SHAKTI and VEGA processor platforms, while the challenge’s SHAKTI hardware and software remain available for developers to reproduce on supported FPGA boards.
Three teams have won the Digital India RISC-V (DIR-V) Grand Challenge, with the results announced during the concluding session of SEMICON India 2026 on 19 September. Organised by Maker Village under the Chips to Startup (C2S) programme of the Ministry of Electronics and Information Technology (MeitY), the challenge attracted 1,236 teams comprising 5,045 participants. The three winning teams received a total prize of Rs 60 lakh.
Meevisai Technologies, representing Team Digital Dawgs from SASTRA University, won the first prize for an autonomous water-surface cleaning robot using the SHAKTI processor developed by IIT Madras. Digiscope LLP from the ER&DCI Institute of Technology, Thiruvananthapuram, took second place with a VEGA-based digital stethoscope, while Zetawave Technologies from the Indian Institute of Science, Bengaluru, secured third place for a VEGA-based forest-environment monitoring system.
Alongside these applications, the SHAKTI project provides a reproducible FPGA platform for developers who want to experiment with the processor architecture. The GC2025 repository includes Ganga, a 64-bit RV64IMACSU implementation, and Yamuna, a 32-bit RV32IMACSU implementation, with support for Artix-7 100T and Nexys Video boards. The repository contains the hardware, software, SDK and bitstream-related resources needed for development.
For a basic Ganga setup, developers can use a compatible Artix-7 100T FPGA board such as the Digilent Arty A7-100T, a Micro-USB connection and a computer running the required Xilinx FPGA development tools. The board’s FPGA provides the programmable fabric in which the SHAKTI processor and its SoC components are implemented. This means the developer does not need a physical SHAKTI processor chip to run the design.
The SHAKTI C-class is a six-stage, in-order RISC-V processor design. In the GC2025 platform, Ganga provides the 64-bit configuration, while Yamuna provides the corresponding 32-bit implementation. The Ganga SoC integrates 256 MB of DDR memory and an 8 KB boot ROM. Its peripheral configuration includes 16 GPIOs, two general-purpose timers, two SPI controllers, two UART controllers and one I2C controller, along with the platform-level interrupt controller, core-local interruptor, FTDI-based debugging interface and Xilinx Ethernet Lite IP.
The processor is implemented as soft IP inside the FPGA. Consequently, the Artix-7 fabric contains the processor logic, memory interfaces and peripheral logic required by the SoC. This also makes the platform useful for hardware-software co-design because the FPGA implementation can be rebuilt when the underlying hardware configuration is changed.
On the software side, developers need the SHAKTI Software Development Kit, the RISC-V toolchain and OpenOCD. The GC2025 repository includes the GCSDK and board-support resources, while its documentation provides instructions for programming SHAKTI onto supported Arty FPGA boards. The SDK also contains example code and sensor-related applications.
After installing the required FPGA tools, the board can be connected to the host computer through its USB interface and the supplied Ganga bitstream programmed into the FPGA. Once the SoC is running, an application can be compiled for the target processor using the RISC-V toolchain. A simple UART application is a practical starting point because it provides a way to verify that the processor, memory and serial communication path are functioning correctly.
OpenOCD provides the debugging path. The SHAKTI development workflow uses OpenOCD together with the RISC-V GNU debugger, allowing compiled programs to be loaded and debugged on the FPGA implementation. Developers can move beyond simply executing an application and inspect processor execution while working with the hardware platform.
The available peripherals also make the board suitable for embedded experiments. Developers can connect sensors and other devices through I2C or SPI, control external circuits using GPIO, work with timers and explore network-connected applications through the available Ethernet interface. The GC2025 software repository also contains examples involving sensor integration, providing a route from a basic processor demonstration to a more complete embedded system.
The FPGA implementation should, however, be treated differently from a fabricated microcontroller or application processor. Its performance and power characteristics depend on the FPGA fabric and implementation rather than dedicated processor silicon. Its value is instead in providing a practical environment for studying RISC-V architecture, SoC integration, embedded software and hardware-software interaction.
The wider SHAKTI ecosystem also has support for Linux on C-class systems, including documentation for running Linux on an Arty A7-100T. However, developers working specifically with the GC2025 Ganga configuration should use the published configuration and documentation when determining operating-system and peripheral compatibility rather than assuming that every SHAKTI configuration has identical capabilities.
The DIR-V Grand Challenge demonstrates how these processor platforms can be used in complete embedded systems, from autonomous cleaning robots to medical and environmental monitoring. For students and developers, the FPGA implementation provides another entry point into the ecosystem: a 64-bit Indian RISC-V processor can be loaded onto an Artix-7 board and used with real peripherals without requiring access to fabricated processor silicon.
For developers specifically interested in fabricated Indian processor silicon, C-DAC’s ARIES v3.0 provides a different route. The board is based on the THEJAS32 ASIC, which incorporates the VEGA ET1031 processor and operates at 100 MHz. C-DAC positions the board for applications including IoT, sensor fusion, smart metering, remote sensing and electronics education.
The two platforms therefore serve different purposes. The SHAKTI GC2025 setup puts a configurable RISC-V processor and SoC onto FPGA fabric, making it suitable for experimentation with processor hardware and software. ARIES v3.0 provides a board based on a fabricated VEGA SoC. Together, they offer different ways for Indian developers and students to explore processor design, embedded systems and indigenous computing platforms.
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