A new neural interface architecture dramatically reduces brain signal data transmission, cutting power demands and improving efficiency for future implantable brain-computer interface applications.
Imec has developed a neuromorphic neural interface architecture featuring a neuromorphic compressive telemetry (NCT) chip that significantly reduces the volume of neural data transmitted while lowering power consumption. Designed for intracortical brain-computer interfaces (BCIs), the approach enables real-time, lossless compression of neural signals, addressing key challenges in bandwidth, energy efficiency and heat generation.
The system replaces conventional fixed-rate sampling with an event-driven technique known as send-on-delta sampling. Rather than continuously recording signals at high frequencies, the chip captures data only when meaningful changes occur in neural activity. This substantially cuts redundant information while preserving the accuracy of recorded brain signals.
To transmit this compressed information efficiently, the architecture combines send-on-delta processing with a ternary packet-based address-event representation (AER) serialiser. Instead of sending numerous small packets, the design groups correlated neural events into compact transmissions. This reduces communication overhead, lowers bandwidth requirements and minimises energy use without sacrificing signal fidelity.
The chip also eliminates the need for complex arbitration circuitry typically required in conventional AER systems. By transmitting events in a controlled sequence, it avoids data collisions while reducing latency and simplifying hardware implementation. Rich multi-bit encoding enables accurate reconstruction of neural waveforms, including low-amplitude spikes.
According to the developers, neural signals are naturally sparse and often occur simultaneously across neighbouring electrodes. The new architecture exploits these characteristics to filter redundant information directly at the source. As a result, fewer data points require transmission, easing processing demands for implantable BCIs.
The design could support future high-channel-count neural implants by extending battery life, reducing device size and limiting heat generation. Such improvements may help enable more practical long-term brain-computer interfaces for neurological research and advanced medical applications.
