The Memory Technology Challenging SRAM

As SRAM reaches its limits, a new memory design could fit more memory on chips, use less power, and reduce the need for external memory.

For decades, static random-access memory (SRAM) has been the standard embedded memory technology in semiconductor chips because it scaled with each new complementary metal-oxide-semiconductor (CMOS) process generation. As manufacturing moved to smaller nodes, SRAM cells also became smaller, allowing designers to integrate more memory into the same silicon area.

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However, this scaling advantage has slowed in recent generations. Around the 5nm node, SRAM density improvements began to stagnate even as logic transistors continued to shrink. One reason is that SRAM had benefited from specialised foundry design rules, often called “push rules,” which enabled more compact bit cell layouts than standard logic cells. As foundries introduced similar optimisation techniques for logic standard cells, logic scaling continued while SRAM had fewer opportunities for further area reduction.

Additional scaling challenges come from the structure of the SRAM bit cell itself. SRAM relies on carefully balanced transistor ratios to maintain stability during read and write operations. At smaller geometries, process variations make maintaining these ratios more difficult, affecting reliability and potentially reducing manufacturing yield.

The slowdown in SRAM scaling has created a growing memory bottleneck for AI accelerators, high-performance processors, and networking chips that require larger amounts of on-chip memory. To compensate, designers increasingly rely on external memory technologies such as dynamic random-access memory (DRAM) and high-bandwidth memory (HBM), but this increases power consumption, latency, and system complexity.

These limitations have driven interest in new embedded memory architectures that offer higher density, lower power consumption, and compatibility with existing CMOS processes. One such technology is gain-cell random-access memory (GCRAM), which aims to overcome SRAM scaling challenges for applications including AI accelerators, high-performance computing, and advanced semiconductor designs.

How GCRAM Differs from SRAM 

The main architectural difference between GCRAM and conventional Static Random Access Memory (SRAM) lies in the design of the memory bit cell. A standard SRAM bit cell typically uses six transistors to store one bit of data, while two-port SRAM uses eight transistors. GCRAM stores one bit using only three transistors in both single-port and two-port implementations. This lower transistor count increases memory density, reduces power consumption, and allows more memory to fit into the same silicon area.

The smaller bit cell is supported by redesigned peripheral circuits that operate the three-transistor cell efficiently while maintaining SRAM-like single-cycle performance without compromising density or power benefits.

Unlike SRAM, which stores data as long as power is applied, GCRAM uses dynamic storage. Stored data must therefore be periodically refreshed, similar to Dynamic Random Access Memory (DRAM) and embedded DRAM (eDRAM), because the smaller three-transistor cell is more susceptible to leakage currents that gradually discharge the stored information.

GCRAM is designed to work within a standard Complementary Metal-Oxide-Semiconductor (CMOS) manufacturing process, unlike many alternative embedded memory technologies that require additional fabrication steps, special capacitors, or other non-standard process elements. To tolerate process variations and leakage without such manufacturing changes, GCRAM co-optimises both the bit cell and the surrounding memory circuitry, improving data retention while preserving high density and low power.

To deliver SRAM-like single-cycle access despite requiring refresh, each memory macro includes a refresh controller, typically implemented in Register Transfer Level (RTL) logic, that performs refresh operations without interrupting normal memory access. The controller can be customised for different applications. For Artificial Intelligence (AI) acceleration workloads, where memory access patterns are often predictable, refresh operations can be scheduled during idle cycles, hiding the refresh process from the processor and avoiding additional latency. In other applications, the refresh strategy can be tailored as long as every row is refreshed within its retention time.

This architecture has been demonstrated across manufacturing nodes from 16 nanometres to 2 nanometres and is expected to remain compatible with future CMOS process generations while continuing to provide higher density and lower power than conventional SRAM.

GCRAM Targets High-Activity Workloads

GCRAM is designed for systems with frequent read and write operations. It becomes more power-efficient than SRAM when memory activity exceeds about 1% to 2%. Below this level, refresh power becomes a dominant factor, making SRAM a more power-efficient choice for such low-activity applications.

In higher-activity workloads, the refresh overhead is less significant, allowing GCRAM to reduce power consumption through lower Read and Write current per bit. This makes it suitable for applications such as AI accelerators and networking systems with continuous memory access.

However, GCRAM is less suitable for small, tightly coupled memories such as L0 and L1 processor caches, where refresh overhead can affect performance and the area savings are limited because the memory arrays are small.

The greatest benefits are in applications that require large memory blocks and frequent memory access. In these systems, GCRAM offers both lower power consumption and a smaller memory footprint.

GCRAM can also increase the amount of memory integrated on a chip. It provides about twice the density of SRAM in the same manufacturing process, enabling larger on-chip memory capacities. This can reduce reliance on external memory such as high-bandwidth memory (HBM) and help reduce data movement bottlenecks between processors and external memory. Its density advantage could become even greater in future process nodes if GCRAM continues to scale better than SRAM.

The impact on chip cost depends on the application. In high-performance systems such as AI processors, the main benefit is fitting more memory into the same chip area, improving performance and power efficiency without increasing die size. In cost-sensitive and low-power applications, GCRAM can maintain the same memory capacity as SRAM while reducing chip size. Because smaller dies generally lower manufacturing costs, GCRAM can reduce fabrication costs in designs where memory occupies a large portion of the chip area. Depending on the application, its benefits include higher memory capacity, lower power consumption, smaller chip size, and lower manufacturing costs.

The Road Ahead

So far, testing has focused on characterising the memory array and achieving high bit yields across a large population of bit cells. Initial soft error testing has been completed, while additional reliability evaluations, including high-temperature operating life (HTOL) testing, are in progress.

The technology is currently being evaluated by established semiconductor companies,  system companies, and hyperscalers developing their own chips. The initial focus is on these companies because they offer opportunities for high-volume production and faster adoption.

Once fully qualified, GCRAM is expected to function as a general-purpose embedded memory technology similar to SRAM, allowing its use across a wide range of applications.

Looking beyond GCRAM, the next challenge in semiconductor memory is increasing memory density while maintaining SRAM-like performance. As AI models and datasets continue to grow, reducing data movement between processors and external memories such as DRAM and HBM will become increasingly important. Future approaches could include 3D stacking of memory bit cells on a single die or vertically stacking multiple memory dies to increase on-chip memory capacity, reduce dependence on off-chip memory, and improve system efficiency for next-generation computing workloads.

GCRAM vs Other Memory Solutions

Key Advantage of GCRAM: GCRAM focuses on memory-intensive applications that require better area efficiency and lower power consumption, while allowing existing memory technologies to continue serving their optimised use cases.

Companies Working on Gain-Cell and High-Density Embedded Memory