Tuesday, April 23, 2024

7nm IC Technology Trends And Challenges (Part 1 of 2)

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Gate-all-around FETs are similar in concept to FinFETs, except that gate material surrounds the channel region on all sides. Depending on design, gate-all-around FETs can have two or four effective gates.

Gate-all-around FETs have been successfully characterised both theoretically and experimentally. These have also been successfully etched onto indium-gallium-arsenide (InGaAs) nanowires, which have higher electron mobility than silicon. InGaAs is a ternary alloy (chemical compound) of indium, gallium and arsenic. Indium and gallium are both from boron group (group III) of elements, while arsenic is a pnictogen (group V) element. Thus, alloys made of these chemical groups are referred to as III-V compounds.

Because these are from the same group, indium and gallium have similar roles in chemical bonding. InGaAs is regarded as an alloy of gallium-arsenide and indium-arsenide with properties intermediate between the two, depending on the proportion of gallium to indium. InGaAs is a semiconductor with applications in electronics and optoelectronics. The graph in Fig. 3 shows 90nm, 65nm, 45nm, 32nm, 22nm, 14nm and 10nm to have around two years gap in every succession.

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Fig. 3: Nanometer versus years

32nm/28nm was an inflection point below which it really was difficult to scale down. Double patterning and then multiple patterning started taking place. FinFET was invented, and now we are looking at gate-all-around and other innovative transistor structures, EUV and so on, to go below 10nm. Definitely, a few of these will have long maturity curves with major production volumes. It needs clever and strategic planning for fabs to reap the benefits from these; these would become cash cows in the long run.

Fabricating transistors is one part of the process, often called front-end-of-line (FEOL) process. Back-end-of-line process is for all interconnections, and there comes the complex part of managing resistance-capacitance.

Again, there are local interconnects at the device level, accomplished by middle-of-line process. Global interconnects are done by back-end-of-line and are prone to resistance-capacitance delays. Today, at lower nodes, back-end-of-line employs multiple patterning, which requires extra deposition and etching with every pattern, thus increasing the cost of production.

Technically, multiple patterning can still be viable at 7nm. However, the industry is looking at extreme ultraviolet (EUV) lithography to reduce that cost. With EUV, back-end-of-line process can be done with single exposure and throughput can be as good as ~150 wafers per hour. But for EUV lithography, foundries are dependent on semiconductor equipment manufacturing companies. It has developed a technology to fabricate test patterns with minimum line width of 1.5nm, which can be used to test metrological equipment with ultra-high precisions. Yield and patterning technologies are important.


Standard architecture of high-performance logic chips these days assumes that all transistors work, and we are talking about chips that would contain several billion transistors each. In terms of manufacturing and reliability, integrated semiconductor devices are amazing and put mechanical devices to shame—billions of components connected in a complicated way, and barring disaster, these things can all work for many years at a time without failure.

To be manufacturable, chip makers need to have the yield of good chips high enough to cover the manufacturing costs at a reasonable price point. That typically means yield rates over at least 30 per cent.

Patterning technology

All chips in recent years and even their prototype 10nm node products are patterned using photolithography, based on a light source with a wavelength of 193nm. Manufacturers have relied on pattern features down to one-twentieth of the free-space wavelength of light, including immersion lithography, optical phase control, exotic photochemistry and multiple patterning.

Finally, it is time to switch to a new light source of 13.5nm wavelength, which is the so-called EUV. This has been in the planning stages for years, with prototype EUV 300mm wafer systems. However, changing to new wavelengths and therefore new processing chemistry and procedures is fraught with challenges.

EUV lithography

EUV lithography represents a major technological advancement for semiconductor manufacturing. Current lithographic techniques utilise deep ultraviolet (DUV) light sources that produce wavelengths of 248nm or 193nm. EUV light used in EUV lithography has a wavelength of 13.5nm, a full order of magnitude shorter. This is important because imaging capabilities or resolutions of a lithography system are proportional to and limited by the wavelength of light used.

EUV remains a consistent challenge, and though manufacturers swear they can solve the power problem, the difficulties are staggering. Gate-all-around is an attractive method for improving transistor performance, but manufacturers are still struggling to hit reliability and dimension challenges. Materials like graphene or carbon nanotubes meanwhile would not debut for a decade or more in complex CMOS logic devices.

EUV light source produces short wavelength light in a system called laser produced plasma. Such light sources utilise a high-power laser to create high-energy plasma that emits short wavelength light inside a vacuum chamber. There are multiple ways that EUV differs, mostly associated with methods to create and transport the short wavelength light.


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