India has built a strong semiconductor design ecosystem, but turning chip ideas into successful products requires much more than engineering. In an interview, Sudeep Shivalli of Synopsys India spoke to Nidhi Agarwal from Electronics For You about the challenges and opportunities shaping India’s chip industry.
Q. What are Synopsys’ main product lines and offerings?
A. Synopsys operates across three major product lines. The first is electronic design automation (EDA), which supports the complete chip design process with artificial intelligence (AI)-driven design automation, from system design, emulation and prototyping to implementation and verification. The company also provides technology computer-aided design (TCAD) tools for device and process modelling, enabling semiconductor manufacturers to simulate transistor behaviour and fabrication processes. These tools help ensure that manufacturing parameters are optimised before production.
The second and third product lines are semiconductor intellectual property (IP) plus simulation and analysis. Synopsys develops IP blocks used in system-on-chip or custom silicon, including interface IPs such as peripheral component interconnect express (PCIe), high bandwidth memory (HBM), universal chiplet interconnect express (UCIe), universal serial bus (USB), mobile industry processor interface (MIPI) camera interfaces, high-speed interconnects, and foundation IP. Its simulation and analysis portfolio provides multiphysics capabilities covering thermal, stress, fluid and structural analysis, supporting the development of digital twin platforms for modelling and optimising complex systems.
Q. How does Synopsys support intelligent and mission-critical systems?
A. As intelligent systems evolve toward physical AI, the industry requires a new engineering approach that combines semiconductor innovation with system-level understanding. Synopsys is uniquely positioned to deliver this through its silicon-to-systems portfolio, enhanced by Ansys simulation technologies. From chip architecture and semiconductor IP to digital twins, multiphysics simulation, and system validation, Synopsys helps customers design, optimise, and deploy safe, reliable, and intelligent products across automotive, industrial, aerospace, and other mission-critical markets.
For example, vehicles contain multiple electronic control units (ECUs) that run on silicon, and manufacturers must determine the right chip architecture based on the workloads of electric vehicles, advanced driver assistance systems (ADAS), and other automotive applications. Synopsys works with original equipment manufacturers (OEMs), Tier 1 suppliers, and semiconductor companies to design, optimise, and virtualise the entire silicon-to-system stack
Q. What does India need to become a full semiconductor manufacturing hub?
A. Semiconductor manufacturing involves multiple ecosystems, including fabrication, outsourced semiconductor assembly and test (OSAT), packaging and design. Building a full-stack semiconductor industry means developing all three areas together. India began this journey through the India Semiconductor Mission (ISM), with an initial focus on OSAT and packaging because those ecosystems can be established faster and have immediate business opportunities.
India’s semiconductor manufacturing ecosystem will take time to scale. Building world-class fabs is only one part of the journey; it also requires the parallel development of supporting industries such as speciality chemicals, gases, materials, equipment, supply chains and engineering services.
India already has a strong semiconductor design foundation built over the last three decades. The next phase is to integrate design, fabrication, packaging, testing, and manufacturing into a cohesive value chain, supported by strategic global partnerships and continued investment.
While significant momentum is underway, creating a resilient semiconductor ecosystem at scale is a long-term endeavour. It is shaped by operational experience, market demand, supply-chain maturation, and continuous learning. With sustained execution, India has the opportunity to evolve from a global semiconductor design powerhouse into a full-stack semiconductor hub spanning design, manufacturing, and advanced packaging.
Q. What role does an EDA company like yours play in the transition?
A. Since the India Semiconductor Mission announced its policies, we have been actively working to strengthen the semiconductor ecosystem. We are part of initiatives such as the design-linked incentive (DLI) scheme and the chip-to-startup program, helping startups and innovators gain access to EDA tools so that they can develop solutions for real-world challenges. We also work closely with academia, industry, and government to support ecosystem growth and encourage semiconductor innovation.
Another key area is workforce development. We are engaged with more than 300 universities, helping shape curricula, conducting faculty development programs, and providing access to industry-standard EDA tools. We have also supported selected university projects through the tape-out (the final stage in chip design where the completed blueprint is sent to a semiconductor foundry for manufacturing) process to foundries, giving students and faculty practical chip design experience. This helps create a talent pool with skills that are better aligned with industry needs and supports the long-term growth of India’s semiconductor manufacturing ecosystem.
Q. What are the biggest challenges in taking a chip from design to production in India?
A. One of the biggest challenges is developing a clear product strategy. Companies need to decide which markets they want to serve, define their product lines, and create a roadmap for scaling their business. While investment opportunities have improved through research and deep-tech funding initiatives, attracting capital still depends on having a strong go-to-market plan. Chip development also requires significant upfront investment, specialised expertise and strong ecosystem partnerships, making it very different from software development.
Another challenge is building a strong domestic market for locally designed chips. Greater adoption across sectors such as transportation, consumer electronics, aerospace, and security can help companies establish sustainable product lines while remaining globally competitive. In addition, although India’s semiconductor manufacturing ecosystem is growing, companies developing advanced chips still rely heavily on global foundries, making international manufacturing partnerships critical for moving designs from concept to silicon production.
Q. What challenges do startups in India face when bringing silicon products from concept to tape-out?
A. The first challenge is securing a strong go-to-market strategy, adequate funding, and ideally an anchor customer who believes in the product idea, as many startups struggle to cross this initial business hurdle. Once that is addressed, finding the right talent becomes critical. Chip development requires engineers with a system-level understanding who can visualise what the chip needs to achieve electronically and translate those goals into silicon, rather than simply executing individual tasks within an engineering project. Another major challenge is managing risks related to time-to-market, tape-out schedules, and execution.
Startups must also secure foundry capacity for fabrication, which is generally manageable for mature-node chips but becomes significantly more complex for advanced-node designs. In such cases, multiple elements must come together, including support from fabrication, packaging, and testing partners. The entire semiconductor value chain must be aligned with the startup’s business commitments and timelines, making coordination across the ecosystem another key challenge that startups continuously work to mitigate.
Q. Where are the biggest opportunities for Indian chip designers today?
A. India has a strong semiconductor design ecosystem with many global chip companies operating large engineering and design centres in the country. These teams are already working on advanced chip designs across areas such as data centres, AI, edge AI, and automotive electronics, creating significant opportunities for engineers and design teams.
From an industry perspective, three major trends are shaping the market: AI, software-defined systems, and silicon proliferation. Silicon proliferation is particularly relevant to India. As more sectors adopt specialised semiconductor solutions, there is growing demand for chips designed for applications such as railways, cameras, ships, industrial equipment, and other locally developed systems. Government initiatives encouraging domestic design and development in these sectors are also creating new opportunities for Indian semiconductor teams to contribute to products designed and built in India.
Q. What technical challenges must new fabs overcome before reaching stable high-volume production?
A. One of the most significant challenges for a new semiconductor fab is achieving and sustaining high manufacturing yield. Yield refers to the percentage of chips on a wafer that meet performance, power, and reliability specifications. Reaching mature yield levels, often above 98 per cent, requires extensive process optimisation, multiple silicon iterations, and continuous learning across the manufacturing flow.
The journey begins with transistor and process technology development, followed by IP enablement, test chip creation, and silicon validation. Data gathered from early silicon runs is used to refine process parameters, design rules, manufacturing recipes, and quality controls. This iterative cycle is essential to improving yield, performance, and overall production efficiency.
Beyond the fab itself, semiconductor manufacturing depends on a highly coordinated ecosystem of equipment, materials, speciality chemicals, gases, packaging, testing, and supply chain partners. Every element must operate with exceptional precision and consistency to achieve stable high-volume production.
As a result, ramping a fab is not simply about installing manufacturing equipment. It is a complex, multi-year process that requires deep engineering expertise, ecosystem readiness, operational discipline, and continuous optimisation. Stable, high-volume production is ultimately achieved through sustained execution, accumulated manufacturing experience, and ongoing collaboration across the entire semiconductor value chain.
Q. How can India balance the demand for mature-node chips and advanced-node technologies?
A. Mature-node and advanced-node chip manufacturing require very different production ecosystems. It is not simply a matter of using the same facilities for both. The equipment, process controls, design requirements, and manufacturing parameters differ significantly. Advanced-node fabrication demands much higher precision and substantially larger investments, while mature-node manufacturing involves a different set of investments and operational controls. In that sense, they are almost like two separate production lines serving different market needs. To balance demand for both, India will need dedicated investments and infrastructure tailored to each segment rather than relying on a single manufacturing approach.
Q. How can government incentives accelerate semiconductor manufacturing while ensuring long-term sustainability?
A. Government incentives are playing an important role, and India has already taken positive steps by introducing strong policies and highlighting the importance of semiconductors as the foundation of electronic systems and digital transformation. The government has helped create momentum across the industry and signaled the strategic importance of building a semiconductor ecosystem.
The experiences of Taiwan and South Korea show that success requires sustained effort over several decades. Taiwan followed a government-led model, while South Korea built its industry through collaboration between the government and large industrial groups. For India, government support must now be complemented by greater participation from private companies. More local manufacturing, stronger industry investment, and a focus on meeting domestic demand will be key to building a sustainable semiconductor ecosystem in the long term.
Q. How can domestic chip production strengthen India’s electronics supply chain?
A. The fabs being set up in India are focused on mature process nodes, which was a deliberate decision. Many chips used across local applications can be designed and manufactured on these mature nodes, allowing a significant portion of domestic demand to be met within the country. This can help reduce dependence on imports and strengthen supply chain resilience. However, achieving this requires more than just building fabs.
Large private companies and industry stakeholders need to assess local consumption patterns, map product requirements, and design and manufacture chips in India. This will help ensure that fabrication facilities operate at full capacity while meeting domestic demand. India is still in the early stages of establishing its manufacturing ecosystem, and collaboration across the entire value chain, including end-user companies, will be essential. Building this ecosystem and creating a self-sustaining supply chain will take time.
Q. Why is advanced packaging becoming so important?
A. Advanced packaging is extremely critical to the future of the semiconductor industry. While innovation continues on the chip design side, significant advances are also taking place in packaging as designs increasingly move toward multi-die architectures and 3D-stacked dies, where multiple chips are stacked and interconnected using advanced technologies. Packaging these multi-die systems is a major challenge, requiring analysis of power delivery, thermal performance, signal integrity, and mechanical stress. One of the key concerns is warpage, where large multi-die packages can deform, potentially impacting performance and reducing chip lifespan. To address these challenges, semiconductor companies are working closely with packaging partners on simulation and analysis. Innovation is happening across packaging materials, substrate design, and system-in-package technologies, making advanced packaging a critical enabler of next-generation semiconductor devices.
Q. How are advanced packaging technologies changing the relationship between design and manufacturing?
A. Advanced packaging technologies have made design and manufacturing much more interconnected. Today, it is a continuous “correct-by-construction” process where both teams exchange data and models throughout development. Design teams provide specific formats and information to packaging engineers, while packaging teams supply models that help designers perform analysis and optimisation. Some improvements are made at the design stage, while others are handled during packaging.
As packaging decisions affect factors such as form factor, pin count, current-carrying capacity, and overall system requirements, packaging must be considered very early in the development cycle, often when the specification or register-transfer level (RTL) is being defined. The package architecture needs to be largely finalised before many design decisions can be completed. As a result, design and manufacturing are no longer isolated functions; they operate as an integrated process with close collaboration from the beginning of the project.
Q. How are EDA tools evolving to support advanced packaging technologies?
A. At Synopsys, EDA tools are evolving to support advanced packaging through capabilities like the 3D integrated circuit (IC) Compiler, which enables multi-die design and workflows with packaging models to define how multiple dies are arranged and integrated, along with simulation and analysis tools that provide multiphysics support including stress, thermal behaviour, and electrical effects like noise, allowing any physical effect that can be modelled to be simulated and thereby providing end-to-end support for advanced package design and analysis.
Q. What verification challenges emerge when moving from single-die design to chiplet-based architectures?
A. The main challenge is ensuring correct system-level behaviour across the full chiplet architecture, including power-up sequencing, die-to-die functional interactions through high-speed interfaces, and workload execution for cloud-level use cases. To address this, hardware-assisted verification is used, where the full chip is modelled on platforms like Zebu before silicon is available. This allows customers to run real workloads pre-silicon, including complex AI and large language models (LLMs) as well as smaller software workloads, and observe system behaviour early. This process, called hardware-assisted verification (HAV), helps identify issues and guide design improvements before tape-out, and continues iteratively until the chip is ready. Once silicon is available, the same workloads can be run again on the actual hardware to confirm real-world performance and correctness.
Q. Will chiplets eventually replace large monolithic system on a chip (SoCs) for most high-performance applications?
A. Yes, in many high-performance applications chiplets are expected to move ahead of large monolithic SoCs. There is also work on wafer-scale approaches where an entire wafer is treated as a single system, especially in data centre use cases. The shift is mainly driven by reuse and the ability to scale product lines more efficiently. However, the choice still depends on whether a customer wants a multi-die solution or a full wafer-scale chip, since wafer-scale systems are expensive to handle and bring several second-order system effects. Overall, for domains like data centres, the trend is clearly toward multi-die chiplet-based designs rather than large monolithic SoCs.
Q. What new design challenges emerge when moving below 3 nanometres (nm)?
A. Moving below 3nm into the angstrom territory fundamentally changes chip design. As transistor density and power density increase, challenges such as thermal management, power delivery, signal integrity, and reliability become significantly more complex. Designers can no longer optimise for power, performance, and area alone; they must simultaneously account for thermal, mechanical, and electrical interactions across the entire system. This is driving greater adoption of AI-driven design automation, multiphysics simulation, and silicon-to-systems co-optimisation to achieve performance, efficiency, and first-pass silicon success.
Q. What EDA innovations are needed for gate-all-around (GAA) transistor architectures, and what technology areas are driving EDA demand in India and globally?
A. EDA innovation for GAA transistor architectures is mainly focused on how libraries are designed and implemented, where IP teams develop embedded memory and logic libraries for different foundries across technologies like fin field-effect transistor (FinFET) and GAA, and the key challenge is ensuring that all foundry-specific design rules are correctly handled during implementation through tooling.
At the same time, major demand for EDA solutions is driven by highly complex and cutting-edge designs, both in India and globally, including advanced reduced instruction set computer machine (ARM)-based systems which are becoming more complex, and high-speed interfaces such as UCIe and advanced memory interfaces that require very fast data transfer. These systems also involve building subsystems with multiple IPs and integrating them with processors, sometimes 20, 30, or even more, while running different workloads, which makes the challenge not just about advanced technology nodes but also about managing increasing system-level complexity, integration, and verification across the full design stack.
Q. How is AI changing the way engineers approach chip design and verification today?
A. AI is influencing many aspects of semiconductor development. The availability of open LLMs has created new opportunities for productivity improvements, workflow automation, and engineering efficiency. Many teams are using AI to streamline tasks, while others are exploring its role in code development and verification. In verification, AI can help improve coverage, find bugs faster, and identify the root causes of system-level issues. AI is also changing collaboration by acting as a complementary agent alongside design engineers, helping teams solve problems more quickly and work more efficiently.
At the same time, applying AI directly to code development and verification brings significant challenges. Semiconductor designs involve substantial investments, and every chip must be thoroughly validated before tape-out. Tape-out is not the finish line; it’s where the real validation begins. Any AI-generated code or verification output must therefore be carefully checked to ensure deterministic results, complete coverage, and reliable operation. As a result, the industry is pursuing both productivity-focused AI applications and AI-driven design and verification, with the latter requiring much higher levels of validation and risk mitigation.
Q. How do you see AI influencing EDA workflows, and how is Synopsys incorporating AI into its product portfolio?
A. AI is set to play a major role in EDA workflows by driving workflow automation and helping engineers manage the growing complexity of advanced chip design. Synopsys was the first company to launch Synopsys.ai, which provides a full-stack AI approach that spans AI copilots, generative AI, agent-based technologies, and ultimately autonomous design capabilities. The industry is increasingly focused on reducing chip development cycles, with many customers targeting a 12-month timeline from specification to silicon validation. Achieving this requires more than simply adding engineering resources; it demands new levels of innovation and productivity. AI helps address these challenges by accelerating design tasks, optimising workflows, and solving complex problems that arise in advanced semiconductor development.
Q. Is AI helping identify design rule violations and verification gaps before traditional sign-off stages?
A. AI is being applied across every stage of the design flow, including sign-off. Sign-off covers areas such as design rule checking (DRC), timing, stress, thermal, noise, and manufacturability verification. AI helps engineers reach the root cause of problems faster, analyse issues more efficiently, identify violations and gaps earlier, and implement fixes more quickly. The goal is to shorten the path from problem identification to resolution, improving productivity across all sign-off and verification domains.
Q. What technical limitations still prevent wider adoption of AI in chip design?
A. From a limitations perspective, the possibilities AI offers are enormous and almost boundless. The challenge is not the technology itself but how it aligns with business needs. Not everyone has unlimited access to compute resources, tokens, and AI infrastructure. Even large companies operate within defined business constraints and guidelines, which determine how AI can be used and deployed. These limitations, driven by business requirements and resource availability, are among the key factors affecting wider adoption.
Q. How close are we to seeing AI-generated RTL become production-ready for complex SoCs?
A. The real measure of readiness is whether companies are willing to trust AI-generated RTL in a chip that will eventually go to tape-out. Today, many tools can generate RTL or verification testbenches using AI, but the industry has not yet reached the point where a complex chip has been fully designed, taped out, and validated using AI-generated code alone. The challenge is not generating the code; it is proving that the functionality is correct and reliable. Validation cycles in semiconductor design are long, compute-intensive, and expensive. Since chip development involves significant financial investment and the resulting products are often used in mission-critical and real-time applications, companies are taking a cautious approach. AI is being explored and validated across different stages of the workflow, but when it comes to code generation, organisations remain careful because any issue at that level can affect the entire chip design process. As a result, AI-generated RTL for complex SoCs is still a work in progress rather than a production-ready reality.
Q. What new skills should semiconductor engineers develop to work effectively with AI-enabled design tools?
A. From an engineer’s point of view, strong fundamentals remain essential. There is no shortcut around understanding how transistors work, how digital design fundamentals and logic gates operate, and what design trade-offs need to be addressed.
At the same time, engineers should avoid becoming purely task-focused and instead develop knowledge of protocols and systems. Since chips ultimately go into applications such as mobile devices, surveillance cameras, and other intelligent systems, engineers need to understand the broader system context and how a design can be improved for its end use. Innovation increasingly happens across domains, which is why fundamentals, systems thinking, and protocol knowledge are all important. The approach to workforce development is also changing. Rather than simply learning how to use a tool, engineers should focus on what they want to achieve with that tool. The key question is not how to use the tool, but what problem they are trying to solve with it, and all engineers should adopt that mindset.
Q. What technology trends will have the greatest impact on semiconductor design over the coming years?
A. If you look at technology nodes, a large portion of chips in the market are still built on mature nodes. Around 60 to 65 per cent of chips use mature nodes, meaning anything 12nm and above such as 12nm, 16nm, 20nm, and up to 28nm. Only about 35 per cent of the market is at the cutting edge, and within that, truly advanced nodes—around 2nm and below—make up just about 2 to 3 per cent. These leading-edge designs are mainly used in high-end data centre applications and mobile applications, where advanced performance is required. This split is already well understood and supported by public data, and it shows how semiconductor design continues to evolve across both mature and cutting-edge nodes rather than shifting entirely to the newest technology.
