Sunday, July 14, 2024

Third DVCon India Bigger and Better than Ever

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image002Two years ago, the long-running Design and Verification Conference and Exhibition (DVCon) expanded from Silicon Valley to Bangalore. The first two events were very successful, building to more than 600 attendees from more than 80 companies and organizations. The third edition of DVCon India will be held September 15-16 at the Leela Palace hotel Bangalore, and it is a must-attend event for design and verification engineers and their managers.

The full program is now available online. The two days are packed with keynote addresses, technical talks and poster sessions, moderated panels, a vendor exhibition, and plenty of time for networking with peers. The keynote speakers include executives from Mentor Graphics, Synopsys, Cadence, Canon and a professor from IIT Madras. Their topics include system-on-chip (SoC) verification, the “Make in India” initiative, and the next big killer app for EDA.


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The technical program includes 39 presentations, 13 posters, 11 tutorials, and two panels, covering a very impressive range of topics. The sessions are divided into two parallel tracks: electronic system level (ESL) and design and verification (DV). Attendees may freely switch back and forth between sessions in both tracks as their interests dictate.

Topics covered in the ESL track include:
• High-level synthesis
• ESL power and energy modeling
• System-level design techniques
• Hardware/software co-design and co-simulation
• System-on-chip (SoC) architecture evaluation
• SystemC TLM2.0

The ESL panel considers how to provide an entry-level vehicle for the Internet of Things (IoT) marketplace. The DV panel speculates on how verification flows may evolve in the future, including the roles of simulation, emulation, and formal technologies. The presentations in the DV track include:
• Universal Verification Methodology (UVM) and SystemVerilog
• UVM coding techniques and UVM reuse
• Verification and debug of IoT devices
• Assertions and formal
• Verification of low-power designs
• Processors and SoCs
• Analog/mixed-signal (AMS) verification
• Acceleration and co-simulation
• Portable stimulus

In between the technical sessions, attendees can visit an exhibition area where vendors will showcase the latest commercial solutions for the technologies discussed in the talks and posters. Last but not least, there are many opportunities for attendees to network with their peers. In addition to the breaks between sessions and lunchtimes, Thursday evening features dinner and entertainment. DVCon India 2016 is sure to be an event that’s both educational and enjoyable. We hope to see you there!



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