Building a chip should not require assembling an entire design ecosystem. A Noida-based startup is developing a browser-based EDA platform that aims to reduce dependence on expensive software and high-performance computing, making semiconductor design more accessible to startups, researchers, and emerging chip companies.
Compcarta, a Greater Noida-based semiconductor startup, has built an end-to-end EDA (electronic design automation) platform aimed at simplifying chip design by addressing high software costs, complex toolchains, demanding computing requirements, and limited access to professional design tools. Designed for enterprises, startups, early-stage design companies, and academic institutions, the platform combines cloud infrastructure or on-premises deployment with a mix of open source and proprietary EDA technologies to reduce the cost and complexity of deploying end-to-end chip design flows.
The company’s EDAcloud platform is also hosted on the National EDA Tool Grid under the ChipIN initiative, making its tools accessible to academic institutions across India. Since its deployment, the platform has attracted nearly 700 academic users and is being explored by 10 startups, with the user base continuing to grow. Founded in 2019, Compcarta spent its initial years on research and technology exploration before beginning product development in 2022. The platform was inspired by the founders’ firsthand experience of the challenges faced by startups, universities, and small engineering teams in accessing professional chip design tools.
Rather than developing individual design tools, the startup chose to build an integrated EDA ecosystem. Its EDAcloud platform supports the complete chip design flow, from schematic capture and front-end verification to RTL-to-GDSII implementation, through a unified interface. EDAcloud supports both browser-based cloud deployment and on-premises installation.
The platform follows a hybrid architecture that combines mature open source EDA technologies with proprietary software developed entirely in-house. According to the company, open source tools provide a strong functional base but require significant improvements in usability, workflow integration, and performance before they can be effectively used in commercial environments. Compcarta has therefore enhanced these tools while developing its own technologies where suitable open source alternatives do not exist.
To improve RTL quality before synthesis, the team developed Assayer to detect coding issues early without relying on commercial lint tools. Another example is QuickCDC, a proprietary clock domain crossing (CDC) analysis engine developed after the team encountered limitations while validating its own RTL-to-GDSII flow. Developed entirely by the in-house engineering team, the tool currently resolves a significant proportion of common CDC violations.
Beyond static verification, Compcarta has also developed CircuitPro for analogue and digital schematic design and Catalyzer for physical implementation, covering synthesis, floor planning, placement, clock tree synthesis, routing, and layout generation.
Compcarta has also developed ATPGcore, a design-for-test (DFT) and automatic test pattern generation (ATPG) solution for fault modelling, test pattern generation, fault simulation, and fault coverage analysis. The browser interface integrates graphical workflows with Linux terminal access, allowing designers to inspect logs, modify scripts, and monitor implementation without leaving the browser.
Alongside its founders’ industry experience, Compcarta’s product development is informed by feedback from semiconductor industry veterans, startup founders, and academic researchers. IIT Delhi is among its early adopters and has used the platform for an entire semester of semiconductor coursework, providing feedback on its usability and functionality.
Operating as a bootstrapped company with a compact engineering team supported by interns and academic collaborators, Compcarta continues to add to its technology portfolio. Its tools are now available through the National EDA Tool Grid, where more than 100 institutions and several Design Linked Incentive (DLI) companies have already begun using the platform. Future developments include an analogue layout tool, a logic equivalence checking (LEC) tool, a System-on-Chip (SoC) generator platform, a learning platform, expanded Process Design Kit (PDK) support, and AI-assisted EDA capabilities.
