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Location: Bengaluru and Hyderabad
Company: Intel
IPG/HSIO is chartered to provide high speed serial link IPs to various internal and external SoCs within the Intel eco-system. Key IPs that we work on include PCI Gen6 and 80 Gbps Type-C USB PHYs.
Analog Design Engineer is responsible for analog circuit Design and corresponding Sign-off Verification (Functional, reliability, Mixed-Signal Verification etc) for custom circuits like CTLE, DCO, DFE, Tx and high speed clocking along with leading teams of junior engineers, driving the closure of macro-blocks and IPs and mentoring junior engineers.
What we are looking for is strong hands-on technical skill in high speed mixed-signal circuit design, initiative, ability to think in terms of the overall system and take the decisions necessary to build a better solution for Intel, ability to work in teams, ability to handle pressure and communicate both up and down the chain effectively.
Objectives of the Position
- Own and deliver the Circuit Design/Sign-off verification of high-speed serial link building blocks.
- Drive Post-silicon electrical validation, post silicon debug and high-volume manufacturing support for the IPs.
- Groom the junior team members towards technical excellence, drive innovation in the team and harvest publications/patents.
- Work with internal stakeholders such as post-silicon validation teams, mask design for circuit implementation and logic design to design the analog/digital interface
- Continuously drive the Turnaround time, robustness of circuit design and area/power of IPs.
Desired Competencies and Experiences
- Experience in working with cutting edge silicon technologies.
- Deep understanding of Circuit design/ physical design of Analog Designs on advanced process technologies.
- Expertise on high speed serial link design. Hands-on experience in blocks like Continuous Time Linear Equalizer (CTLE), Digitally Controlled Oscillator (DCO), Decision Feedback Equalizer (DFE), NRZ/PAM-3/4 Transmitter and high speed clocking.
- Expertise in working with post-silicon test engineers.
- Expertise on Reliability aware design and familiarity with Aging and RV tools. Ability to design floor plan and routing in Layout.
- Good grasp on Industry standard tools such as Cadence design Environment (ADEXL or Virtuoso) Knowledge of DRC, LVS, and post-layout extraction tools etc.
- Familiarity with RTL behavioral coding and simulations, timing extractions of custom blocks
- Strong communicator and proven leadership experience, self-driven, proactive nature to own and deliver high quality end to end Analog designs
- Fast learner, good problem-solving skills, multitasking ability and attention to quality and detail.
- Experience with MATLAB and serial link system analysis will be a major plus.
Qualifications
Education: BS/MS – EE/CS and 10+ Years of industry experience.
