APPLY HERE
Location: Ahmedabad
Company: PierSight
Key Responsibilities
- 2-4 years of hands-on experience in implementing designs on FPGA
- Strong expertise in RTL coding of complex designs using Verilog/SV
- Expertise in all aspects of FPGA design: constraint definition, synthesis, floor planning, P&R, Timing closure
- Early architectural/performance exploration through micro-architectural definition and design
- Optimise the design to meet power, performance, area and timing requirements
- Run unit-level testing to deliver quality code to the Design Verification Team
- Create well-written block-level design documentation
- Write testbench and sequences in SystemVerilog.
- Familiarity with lab equipment
- Familiarity with interface protocols (PCIE, Ethernet)
- Knowledge of the latest FPGA architectures and partitioning designs across multiple FPGAs
- Exposure to scripting languages
Preferred Experience
- Hands-on experience with FPGA design suite Libero
- Tcl/perl/python scripting languages
- Good hardware and software debugging skills
- Experience running quality checks such as CDC
- Experience in synthesis, static timing analysis
- Experience with verification and UVM is an added advantage.
- Experience with FPGA Hardware design is an added advantage
