Company: Analog Devices
Analog Devices (NASDAQ: ADI) designs and manufactures semiconductor products and solutions. We enable our customers to interpret the world around us by intelligently bridging the physical and digital worlds with unmatched technologies that sense, measure and connect.
- Architect and Design key digital blocks in high speed SoCs
- Develop optimal micro-architecture by analyzing power, performance and area tradeoffs
- Develop timing constraints, run lint, synthesis and Static-timing-analysis tools – both for micro-arch feasibility analysis in initial stages and for timing signoff by working closely with DFT and PnR teams.
- Review DV test-plans, code and functional coverage by working with DV team for quality DV signoff.
- Contribute to module architecture and block level specification by working with Chip architect
- Collaborate with marketing, system applications teams for product/feature definition
- Minimum BE/BTech degree in Electrical/Electronics
- 6 -12 years of digital logic design and hands-on RTL coding experience using Verilog and SystemVerilog
- Must have worked with product development teams and the designs must be realized in Silicon (ASIC tapeouts, *not* FPGA)
- Hands-on experience with developing timing constraints and running state-of-the-art Synthesis and Static timing analysis tools
- Experience with Lint, CDC, formal equivalence, ECO flows and scripting
- Good Knowledge in Processor/SoC architecture, DSP fundamentals
- Good verbal and written communication skills to work effectively with teams spread geographically
- Ability to technically mentor a few junior engineers
- Experience with participating in Post Silicon issue debug is a definite plus