High Speed PCB Design For Electromagnetic Compatibility (Part 1 of 5)

Reduction of ground track inductance

The inductance of a PCB trace is directly proportional to its length. This can be used to advantage by minimising the length of critical traces that carry this high transient current. A further reduction can be achieved by increasing the width of the power supply traces.

However, the inductance of a track is inversely proportional to the log of track width. Hence it is difficult to achieve a large decrease in inductance. So rather than dimensions of the tracks, it is the track layout that is the single-most-influencing factor towards achieving the goal of decreased track inductance.

Now it is known that if two identical tracks are in parallel, the equivalent inductance will be halved (if we neglect the mutual inductance) and reduced to a quarter if four tracks are in parallel. However, there is a limit to this because if the tracks are closely placed, the mutual inductance approaches the self inductance and there is no net reduction of inductance. But if the tracks are placed at a distance twice their width, then a 25 per cent reduction in inductance can be achieved.

Thus, in a good high-speed design, it is required to provide as many alternate parallel paths to the ground currents as possible. If this concept is extended without limit, it would mean an infinite number of parallel paths that can be approached by using a ground plane. Multi-layer boards, which use an entire plane as ground, can drastically reduce such problems in one fell swoop.

But if one is constrained to use a two-layer board, this effect can be achieved to some extent by using a gridded ground system (Fig. 1). A good rule to follow could be to have a ground track beneath each IC along its length. The vertical spacing would be equal to the length of each IC. The vertical and horizontal traces can be on opposite sides of the board, the tracks being connected at each crossing by printed-through-hole method.

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In a typical two-sided board with 15 ICs, it has been found that the ground noise voltage decreases to a tenth when gridded ground system is used. Hence all digital PCBs should have a gridded ground plane.

Reduction of loop area

Another method of reducing the inductance is to reduce the area of the loop enclosed by current flow from Vcc to ground. A large open loop (as compared to track dimensions) like that shown in Fig. 2(a) is an efficient radiator of high-frequency currents and the circuit will also be susceptible to externally generated magnetic fields.

For two identical parallel tracks, one for power (Vcc) and the other for ground, which carry currents in the opposite directions, the total inductance (Lt) is given by the expression:
Lt = 2 (L–M)
where L is the inductance of each track and M is the mutual inductance.

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Now, if mutual inductance is maximised by keeping the Vcc and ground tracks close together, the effective inductance will be reduced to almost half. Ideally, the Vcc track should follow the ground track on the PCB. This greatly reduces track length, and also the reduced loop area greatly reduces associated emissions and susceptibility issues.

Fig. 2(a) shows a poor PCB layout while Fig. 2(b) shows an improved PCB layout. By reducing loop area we have reduced track length and associated track impedance, and by doing so we have achieved a reduction in emissions and susceptibility