What if semiconductor chips could learn, adapt and correct their own errors? Pratap Narayan Singh of Vervesemi speaks to EFY’s Nidhi Agarwal about building intelligent analog IP, integrating machine learning into silicon, and taking Indian semiconductor innovation to global markets.
Q. What does your company do?
A. We are a fabless semiconductor company. That means we design and own the intellectual property (IP) for semiconductor chips, including their architecture and product design, but we do not manufacture them in-house. Instead, we work with commercial semiconductor fabrication plants (fabs) to produce our chips while managing the entire supply chain, from design through to production and delivery.
Founded in 2017, we are now a relatively established company. However, under the Government of India’s policy, semiconductor companies can retain startup status for up to 15 years because product development typically takes two to three years or longer to move from design to market. So, despite our maturity, we continue to qualify as a startup within this framework.
Q. What kind of products do you make?
A. We specialise in analogue signal chains and digital signal processing. Our portfolio includes more than 140 IPs, which we have been licensing internationally for the past eight years. Alongside IP licensing, we develop semiconductor integrated circuits (ICs) for industrial electronics applications such as telecom, motor control and energy metering. Our customers include IC manufacturers, motor manufacturers, sensor manufacturers, and companies in the avionics and aerospace sectors, including aircraft, drone and satellite manufacturers.
Q. Why do companies buy your IP instead of building everything themselves?
A. A semiconductor chip is made up of many functional ‘blocks’, such as a central processing unit (CPU), clock generation and signal processing components. Rather than designing every block themselves, many companies license proven IP from specialist suppliers. For example, Arm licenses CPU processor IP that semiconductor companies integrate into their chip designs. Likewise, we provide signal-chain IP, while other suppliers may provide clock-generation IP. A complete chip is therefore assembled by combining multiple IP blocks from different vendors. This allows semiconductor companies to focus on their core expertise instead of investing time and resources in developing every building block from scratch.
Q. What innovation are you bringing to analogue and digital signal processing?
A. We are the only company in India licensing pure-play analogue IP globally, with customers in China, Taiwan, South Korea and Japan. Our innovation combines advanced analogue design with machine learning to improve performance while reducing silicon area, making semiconductor products more efficient and competitive. As a result, several international customers license our IP and integrate it directly into their semiconductor designs.
Q. Is the IP you are talking about a hardware product or a software product, and what exactly does it do?
A. It is a complete hardware product. The IP combines analogue and digital circuitry on a single semiconductor chip and incorporates machine learning algorithms to create a digital model of the analogue subsystem.
This model continuously learns the characteristics of the silicon and identifies imperfections that arise during analogue processing. It can detect degradation not only during manufacturing but also later in the field due to ageing, degraded power supplies or changing reference signals.
Once these imperfections are identified, the system adaptively corrects them in real time. As a result, traditionally complex analogue challenges become much easier to manage while overall system performance, reliability and efficiency improve significantly.
The same technology also improves manufacturing yield, enhances testability and introduces fail-safe capabilities. For example, it can predict when a chip is likely to fail and warn against deploying it. In effect, the machine learning layer becomes the intelligence behind the analogue signal chain, making it more robust throughout its operational life. Our IP is not a block—it is a self-learning signal chain
Q. How is machine learning implemented at the silicon level?
A. While the implementation is proprietary, the underlying principle is straightforward. Every time the chip powers up, it creates a digital model of the analogue subsystem. That model enables the system to understand where errors or imperfections are likely to occur and correct them dynamically.
Because the model is rebuilt each time the device starts, it continuously adapts to process variations, ageing and hardware degradation. If a problem falls outside the system’s ability to compensate, it flags the IP as unreliable instead of allowing incorrect operation.
A useful analogy is a car that warns the driver of a critical fault before a journey begins. Rather than allowing a failure to occur unexpectedly, the system alerts the user before the chip is put into service.
Q. How is machine learning integrated into the analogue signal chain?
A. Machine learning (ML) runs on tightly coupled digital hardware that works alongside the analogue subsystem. Rather than relying on adaptive analogue circuitry alone, the analogue and digital domains function as a single integrated system, with the digital logic performing the ML computations while continuously interacting with the analogue signal chain.
Q. How does the system collect training data?
A. The learning process is largely self-generated. Instead of relying solely on external inputs, the system generates its own stimuli and input vectors, enabling it to iteratively calibrate itself against predefined target parameters. This self-learning approach enables continuous optimisation without requiring extensive external calibration data.
Q. Do you see future versions integrating even more digital processing or edge AI capabilities?
A. Yes. This trend has been evolving for many years. Digital-assisted analogue design has continued to expand since the beginning of the millennium, and we expect even greater integration of digital processing and edge artificial intelligence (AI) capabilities within future semiconductor chips.
Q. What ADC and data-converter architectures do your sensors and metering solutions use?
A. We have a broad portfolio of analogue-to-digital converter (ADC) IPs, covering almost every ADC architecture across our product stack. Our solutions support applications spanning an extremely wide frequency range, from hertz-level sensing and energy metering to gigahertz-scale data conversion. Notably, we are the only company in India developing gigahertz converters, and only a handful of companies worldwide operate at that level.
Q. What specific analogue IP blocks do you offer beyond ADCs and DACs?
A. Our portfolio extends well beyond ADCs and digital-to-analogue converters (DACs). We also develop clock-generation solutions, variable gain amplifiers (VGAs), programmable gain amplifiers (PGAs), filters, and a wide range of sensors, including temperature, process, supply and bridge sensors. Together, these building blocks enable customers to assemble complete analogue signal chains tailored to different semiconductor applications.
Q. What types of parameters in an analogue front-end can be dynamically tuned by learning algorithms?
A. Almost any parameter within an analogue circuit can be dynamically optimised through learning algorithms. In principle, optimisation can extend down to individual transistors. However, there is a practical trade-off because increasing the number of parameters being optimised also increases the size and power consumption of the learning engine. In practice, we optimise a substantial portion of an IP block, typically around 50% to 75% of the circuit, achieving significant performance gains without making the learning system unnecessarily large or power-hungry.
Q. What are the main architectural differences between your analogue front-end and conventional sensor interface ICs?
A. Conventional sensor interface ICs are designed for fixed performance and gradually degrade because of ageing, environmental conditions and process variation. Once performance falls below acceptable limits, they are often replaced.
Our analogue front-end (AFE), by contrast, is adaptive and self-correcting. Rather than allowing performance to drift over time, it continuously calibrates itself to maintain the original level of accuracy throughout its operating life.
The AFE also compensates for fabrication-level imperfections. Achieving very high precision, such as with a 20-bit ADC, typically requires extremely tight manufacturing tolerances because even small process variations can degrade performance. Our architecture creates an internal digital model of the fabricated circuit during start-up, analyses the actual behaviour of transistors and circuit elements, estimates the resulting errors and then applies correction mechanisms to compensate for them. This enables high precision even under imperfect fabrication conditions.
Q. If a component is incorrect, how does the system correct it? Does calibration mean replacing the component?
A. No. Calibration is entirely digital and does not involve replacing hardware. The system already knows the expected digital output. If, for example, the correct value is 100 but the converter produces 95 or 99, it recognises the deviation and digitally compensates to restore the correct output. The hardware itself remains unchanged. Instead, the system continuously applies digital corrections that compensate for imperfections within the analogue circuitry.
Q. At what stage are these errors detected?
A. Errors can be detected both immediately after fabrication and later during field operation. If an issue appears during production testing, it is generally associated with fabrication. If it develops later, it is more likely to result from ageing or long-term operation. From a practical standpoint, however, the source of the error is less important than ensuring the system either corrects it or reliably reports when correction is no longer possible. If compensation reaches its limits, the system flags the failure rather than allowing unreliable operation.
Q. How do you decide the topology or architecture for critical analogue IPs, and how do you optimise them for low power without sacrificing performance?
A. Architecture selection is entirely application-driven. Different applications prioritise different performance parameters. For example, energy metering and weighing systems demand exceptional precision and low noise, whereas cellular base stations place greater emphasis on bandwidth, speed and dynamic performance. Consequently, there is no universal architecture suitable for every application. Power efficiency, however, is a requirement across virtually all markets. Traditional analogue design often compensates for process variability by using larger devices, which increases capacitance and power consumption. Because our machine learning-based design methodology manages variability more effectively, we can frequently use smaller devices that are inherently faster and more power efficient. The system also enables intelligent trade-offs between power, yield, precision and speed, allowing each IP to be optimised according to its intended application rather than a fixed design target.
Q. What key performance metrics do you use to evaluate your IPs?
A. The principal performance metrics include linearity, noise, bandwidth, power consumption and temperature stability. Depending on the application, we also evaluate parameters such as accuracy, speed, efficiency, reliability and overall robustness under different operating conditions.
Q. How do your IPs compare with competing solutions?
A. Some of our IPs have no direct global competitors. For others, the differentiation is significant. Certain gigahertz converters consume nearly five times less power than comparable solutions, while some IPs occupy up to ten times less silicon area than conventional market offerings. These are delivered as hard IPs ready for customer integration.
Q. How easily can your IPs be integrated into system-on-chips (SoCs) or multi-die systems?
A. Analogue integration always requires careful attention because analogue circuitry is highly sensitive to power integrity, noise and overall system conditions. To simplify integration, we provide comprehensive design guidelines covering critical design practices and potential pitfalls. With appropriate implementation, analogue IP can be integrated successfully even into highly complex SoCs manufactured on advanced technology nodes such as 8nm.
Q. Can your IPs be customised for different process nodes, voltages or performance targets?
A. Yes. Customisation is a routine part of our business because customers use different foundries, fabrication processes and performance specifications. We regularly adapt our IPs to meet specific voltage, process-node and performance requirements. Machine learning also helps us manage challenges such as process variation, device mismatch and temperature effects by modelling these variations during design and optimisation, allowing us to deliver consistently high performance across different manufacturing environments.
Q. What design challenges have you faced in analogue systems, and how did you resolve them?
A. Analogue design is much more than circuit design. It combines architecture, functionality, and the ability to solve real customer problems. One of the biggest challenges is testability. When a customer integrates an analogue chip onto a board, and something goes wrong, it is often difficult to determine whether the fault lies in the chip or elsewhere in the system. Unlike digital systems, where logic can be verified systematically, analogue circuits depend on transistor-level behaviour, making fault isolation significantly more complex. Manufacturing scalability presents another challenge. When producing millions of chips, testing every device individually for extended periods is impractical. Our focus has therefore been on improving diagnostics, increasing testability and streamlining validation. These capabilities are particularly important in industries such as automotive and aviation, where reliability is critical. By designing with redundancy, fault anticipation and robust diagnostics from the outset, we have made our analogue products more reliable, practical and easier for customers to deploy.
Q. Since analogue testing is usually difficult, how do you test and validate your systems and IPs?
A. Although we are a fabless company and do not own manufacturing facilities, we have a fully equipped in-house testing and characterisation laboratory supported by our complete in-house research and development (R&D) team. This allows us to carry out testing, validation, and characterisation internally using sophisticated equipment before products enter production.
Q. What were the major roadblocks during development, and how did you overcome them?
A. The greatest challenge has simply been the time and persistence that research demands. Developing deep-tech products does not happen overnight. It requires continuous iteration, learning and refinement. Since founding the company eight years ago, we have developed multiple generations of the same core technology. Each generation has addressed limitations in the previous version while improving performance and capability. That iterative approach has enabled us to overcome technical challenges steadily rather than trying to solve everything at once. We see this as a continuous journey, with significant opportunities for further improvement over the coming decade.
Q. What unexpected failures or behaviours did you encounter during silicon bring-up?
A. Silicon bring-up is a normal stage of semiconductor development. Given the complexity of modern chips, encountering issues during initial silicon validation is expected. Our approach is to analyse the behaviour, identify the root cause and implement the appropriate corrections. Fortunately, we have not experienced any major failures that prevented products from succeeding. Most issues have been routine debugging and optimisation that naturally occur during semiconductor development.
Q. What are the main challenges of designing analogue IPs at 8nm?
A. Designing analogue IPs at 8nm introduces several challenges because advanced FinFET technologies, while providing exceptional transistor density and scaling, also make analogue behaviour more difficult to predict. Engineers must deal with increased crosstalk, more complex small-signal behaviour and transistor characteristics that are harder to model accurately. Extracting the full performance benefits of these advanced nodes therefore requires sophisticated design techniques that compensate for these non-ideal effects.
Q. How do you guarantee long-term reliability and ageing performance in 8nm analogue IPs?
A. Reliability begins during the design stage. Our machine learning-based reliability framework analyses silicon behaviour during production and identifies parameter margins that could influence long-term ageing. If certain parameters operate too close to their limits, the system flags those devices as having a higher risk of degradation over time.
This enables customers to grade devices according to their expected operating lifetime. For example, some products may be suitable for applications requiring a three-year service life, while others, with larger reliability margins, can operate reliably for ten years or longer.
Rather than applying a single standard to every device, customers can match products to the reliability requirements of specific applications.
Q. How do you select the right manufacturing node and foundry partner?
A. The choice of fabrication node and foundry depends entirely on the application’s performance requirements and cost targets. Those two factors determine the most appropriate manufacturing technology and fabrication partner for each product.
Q. Is there a story behind starting the company and the meaning of its name?
A. There was no single defining moment that led to the company’s creation. My co-founder, Rakesh, and I had worked at several multinational semiconductor companies and accumulated extensive industry experience. Eventually, we wanted to build something of our own, something rooted in India and recognised globally for technological excellence.
That ambition became the foundation of the company. The name ‘Vervesemi’ combines ‘Verve’, meaning ‘life’, with ‘semi’, short for ‘semiconductor’. Since semiconductors originate from silicon derived from sand, the idea is that we ‘put life into semiconductors’. In other words, we make sand come alive.
Q. What challenges do Indian semiconductor startups face when scaling analogue IC production globally?
A. One of the biggest challenges is achieving cost competitiveness. Large global semiconductor companies have far greater negotiating power with foundries, suppliers and manufacturing partners, enabling them to secure better pricing and commercial terms. Indian startups, by comparison, are relatively small players and therefore lack similar leverage across the supply chain. As a result, they must compete with established companies that already benefit from significant economies of scale, making global expansion both challenging and capital intensive.
Q. Is the analogue IP market already mature?
A. The analogue IP market is well established and mature. However, our strategy extends beyond analogue IP licensing into the much larger mixed-signal products market, which represents an opportunity worth several tens of billions of dollars. Until now, most of our revenue has come from exporting IP, reflecting our export-focused business model. Beginning this year, we are also generating revenue from our semiconductor product business, marking the next phase of our growth.
Q. Which industries have benefited the most from your analogue IPs?
A. Analogue IP is fundamental to almost every electronic system, making it relevant across a wide range of industries. However, the greatest adoption has been in industrial electronics and telecommunications, where performance, reliability and efficient system integration are especially critical.
Q. What are the biggest challenges as you continue to scale?
A. Our immediate priority is expansion. We are preparing to launch multiple semiconductor products while simultaneously strengthening our supply chain, expanding our sales and distribution network, and enhancing customer support. Managing these parallel priorities while maintaining technological leadership is our biggest challenge as we grow.
Q. Does your company receive government support?
A. Yes. We were the first company to be recognised under the Design-Linked Incentive (DLI) Scheme introduced by the Ministry of Electronics and Information Technology (MeitY). We were also the first company to receive funding under the programme.
In addition, we are among the first companies entrusted with developing motor-control semiconductor products for India, reflecting growing confidence in indigenous semiconductor capabilities.
Q. How do you work with academia and industry?
A. We already collaborate with several Indian Institutes of Technology (IITs), both on research and for developing industry-ready talent. These partnerships help us train engineers in technologies that are directly relevant to semiconductor product development.
Beyond academia, we remain open to new partnerships with customers, distributors, vendors and technology collaborators. Rather than targeting a specific profile, we evaluate opportunities based on the value they can create for both sides.
Q. Where are you investing for future growth?
A. As a deep tech company, sustained investment in R&D will always remain our highest priority. However, technology alone is not enough. We are investing equally in market development, customer relationships, sales and distribution capabilities, and customer support. Building all these capabilities together is essential for long-term growth.
Q. In which areas do you see the greatest potential for future improvement?
A. Technology evolves exponentially rather than in small linear steps. Whenever a technology continues to improve at that pace, it creates opportunities for entirely new capabilities. Once that exponential progress slows, it usually indicates that the technology has reached saturation and requires a breakthrough to begin a new growth curve. That principle applies equally to bandwidth, power efficiency, calibration and other aspects of analogue design. Rather than aiming for incremental improvements of 5-10%, the objective is to achieve exponential gains through continuous innovation.
Q. How do you see AI-assisted analogue design evolving over the coming years?
A. AI is already becoming an integral part of analogue design. In many systems today, machine learning serves as an inference and optimisation engine, helping designers improve performance and compensate for process variations.
Over time, these capabilities will become significantly more sophisticated, enabling increasingly complex design decisions and higher levels of automation. The evolution of AI-assisted analogue design is therefore not about introducing an entirely new concept, but about expanding capabilities that are already transforming semiconductor development.
Q. What new sensing or control applications could benefit most from intelligent analogue chips?
A. Intelligent analogue chips have the potential to unlock applications that are difficult, or even impossible, with conventional analogue technology. By continuously compensating for process variations, ageing, temperature changes, supply fluctuations and manufacturing imperfections, they provide a far more robust foundation for future electronic systems.
Once these capabilities become widely available, system designers will be able to build entirely new generations of sensing and control applications on top of them. Innovation often depends on the capabilities of the underlying hardware. If that foundation improves, new applications naturally follow.
The principle is similar to imaging systems. If the sensor itself is poor, no amount of Artificial Intelligence can fully recover the missing information. As the saying goes, ‘garbage in, garbage out.’
