A new chip process moves into early production, with changes in speed, power use, and heat control, and new transistor and interconnect designs for future scaling.
Intel Foundry has placed its Intel 18A-P process into risk production, marking a key milestone in its 18A family as the company pushes ahead with its leading-edge manufacturing roadmap. The update was shared at the 2026 VLSI Symposium, where Intel also detailed performance gains, transistor innovations, and future research directions.
The company claims that 18A-P delivers 9% higher performance at iso-power or 18% lower power at iso-performance compared to Intel 18A, along with improved thermal behavior and expanded design flexibility. The company also confirmed the node remains design-rule compatible with Intel 18A, allowing reuse of existing IP and design flows.
Intel Foundry engineers highlighted several architectural improvements. A new Power Boost transistor option introduces a dual-contact, low-resistance design to increase drive current and frequency. The process also shows 20–40% lower thermal resistance, 10–30% reduced via resistance, improved PMOS mobility through strain engineering, and additional transistor tuning options, including a fifth logic Vt level between ULVT and LVT.
The company also reported continued scaling benefits from gate-all-around (GAA) transistors and backside power delivery (BSPD), first introduced in Intel 18A. The company cited 11% routed area reduction, 10× lower dynamic voltage droop, up to 6% frequency gains, and more than 15% reduction in dynamic power. Silicon results from CPU cores showed around 30% higher frequency at low voltages (~0.5V), along with reduced IR drop and better efficiency.
Beyond near-term process improvements, Intel presented early research into future technologies. These include CFET devices with vertically stacked transistors at a 45nm gate pitch, 300mm wafer-level GaN and silicon integration for combined power and logic systems, and ruthenium-based interconnects with airgap structures that reduce capacitance by up to ~35% compared to copper.
The company said these efforts are aimed at extending semiconductor scaling beyond current transistor and interconnect limits while improving performance and energy efficiency for future computing systems.
