Delivering up to 5X faster time-to-market, enhanced power-performance-area targets, and advanced data analytics, this innovation promises to tackle rising chip complexity and engineering shortages with unprecedented efficiency.
Cadence has launched Cadence Cerebrus AI Studio, the industry’s first agentic AI, multi-block, multi-user system-on-chip (SoC) design platform, revolutionizing chip design by accelerating SoC time-to-market by up to 5X. This breakthrough addresses the increasing complexity of semiconductor chips, which now contain trillions of transistors and demand high-performance computing while meeting stringent power, performance, and area (PPA) targets under tight schedules and limited expert resources.
Building on the company’s Intelligent System Design strategy, Cerebrus AI Studio advances beyond the 2021 Cerebrus Intelligent Chip Explorer by using cutting-edge agentic AI technology to autonomously manage entire SoC or subsystem implementation flows. Unlike previous tools that focused on optimizing single blocks with multiple designers, this platform enables a single engineer to design multiple blocks simultaneously, drastically improving productivity.
Key features include:
- Intelligent Agentic AI Workflows: AI-driven design optimization delivers superior PPA and faster design closure.
- Multi-Block, Multi-User Infrastructure: Centralized platform supports multiple blocks designed by a single engineer, maximizing SoC implementation efficiency.
- Hierarchical Design Optimization: Top-block co-optimization reduces manual effort and accelerates closure.
- Advanced Data Analytics: AI-powered analytics identify bottlenecks and critical paths for quicker debugging.
- Customizable Live Dashboard: Enhances collaboration and knowledge sharing, boosting productivity exponentially.
The platform features autonomous AI agents capable of making multi-step decisions based on high-level objectives, integrated with Cadence’s Innovus+ RTL synthesis and implementation environment. It offers fully automated design realization with Python scripting and a large language model (LLM) AI assistant.
Early adopters like Samsung Semiconductor India Research and STMicroelectronics report PPA improvements of 8-11%, 4X productivity gains, and faster design convergence. They highlight features such as live dashboards, smart model replay for transfer learning, and advanced analytics as transformative tools.
Chin-Chi Teng, Cadence’s Digital & Signoff Group SVP, emphasizes that Cerebrus AI Studio addresses engineering workforce shortages while delivering unmatched PPA and design speed, marking a generational shift in chip design driven by agentic AI.
